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Details, datasheet, quote on part number:5962-9326101M2A
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Datasheet text preview:
UC1854 UC2854 UC3854
High Power Factor Preregulator
FEATURES
· · · · · · · · · · · Con trol Boost PWM to 0.99 Power Factor Limit Line Current Distortion To <5% World-Wide Operation Without Switches Feed-Forward Line Regulation Average Current-Mode Control Low Noise Sensitivity Low Start-Up Supply Current Fixed-Frequency PWM Drive Low-Offset Analog Multiplier/Divider 1A Totem-Pole Gate Driver Precisio n Voltage Reference
DESCRIPTION
T he UC1854 provides active power factor correction for power systems that otherwise would draw non-sinusoidal current from sinusoid al power lines. This device implements all the control functions n ecessary to build a power supply capable of optimally using available p ower-line current while minimizing line-current distortion. To do this, the UC1854 contains a voltage amplifier, an analog multiplier/divider, a current amplifier, and a fixed-frequency PWM. In addition, the UC1854 contains a power MOSFET compatible gate driver, 7.5V refe re nce, line anticipator, load-enable comparator, low-supply detector, an d over-current comparator. T he UC1854 uses average current-mode control to accomplish fixedfreque ncy current control with stability and low distortion. Unlike peak c urren t-mode, average current control accurately maintains sinusoidal line current without slope compensation and with minimal response to no ise transients. T he UC1854's high reference voltage and high oscillator amplitude minimize noise sensitivity while fast PWM elements permit chopping freque ncies above 200kHz. The UC1854 can be used in single and three phase systems with line voltages that vary from 75 to 275 volts a nd line frequencies across the 50Hz to 400Hz range. To reduce the b urden on the circuitry that supplies power to this device, the UC1854 features low starting supply current. T hese devices are available packaged in 16-pin plastic and ceramic du al in-line packages, and a variety of surface-mount packages.
BLOCK DIAGRAM
UDG -92055
6/98
UC18 54 UC28 54 UC38 54 ABSOLUTE MAXIMUM RATINGS
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . GT Drv Current, Continuous . . . . . . . . . . . . . GT Drv Current, 50% Duty Cycle. . . . . . . . . . Input Voltage, VSENSE, VRMS . . . . . . . . . . . . . Input Voltage, ISENSE, Mult Out . . . . . . . . . . . Input Voltage, PKLMT . . . . . . . . . . . . . . . . . . Input Current, RSET, IAC, PKLMT, ENA . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . . . . . . . . 35V . . . . . . . . . . . . . . . 0.5A . . . . . . . . . . . . . . . 1.5A . . . . . . . . . . . . . . . . 11V . . . . . . . . . . . . . . . . 11V . . . . . . . . . . . . . . . . . 5V . . . . . . . . . . . . . . 10mA . . . . . . . . . . . . . . . . 1W . . . . . 65oC to +150oC . . . . . . . . . . . . . +300oC
Note 1: All voltages with respect to Gnd (Pin 1). Note 2: All currents are positive into the specified terminal. Note 3: ENA input is internally clamped to approximately 14V. Note 4: Consult Unitrode Integrated Circuits databook for information regarding thermal specifications and limita-
CONNECTI ON DIAGRAMS
DIL16 & SOIC-16 (To p View) J, N & DW Packages PLCC-20 & LCC-20 (Top View) Q & L Packages
PACKAGE PIN FUNCTION
FUNCTION PIN
N/C Gnd PKLMT CA Out ISENS E N/C Mult Out IAC VA Out VRMS N/C VREF ENA VSENS E RSET N/C SS CT VCC GT Drv
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Unless otherwise stated, VCC=18V, RSET=15k to ground, CT=1.5nF to ground, PKLMT=1V, ENA=7.5V, ELECTRI CAL CHARACTERISTICS VRMS=1.5V, IAC=100µA, ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=7.5V, no load on SS, CA Out, VA Out, REF, GT Drv, 55oC
PARAMETER OVERALL Supply Current, Off Supply Current, On VCC Turn-On Threshold VCC Turn-Off Threshold ENA Threshold, Rising ENA Threshold Hysteresis ENA Input Current VRMS Input Current
UNITS mA mA V V V V µA µA mV nA dB V mA µA
ENA=0V VRMS=5V
VOLTAGE AMPLIFIER Voltage Amp Offset Voltage VA Out=5V VSE NSE Bias Current Voltage Amp Gain Voltage Amp Output Swing Voltage Amp Short Circuit Current VA Out=0V SS Current SS=2.5V
25 100 0.5 to 5.8 20 14
5 6
2
UC18 54 UC28 54 UC38 54
Unless otherwise stated, VCC=18V, RSET=15k to ground, CT=1.5nF to ground, PKLMT=1V, ENA=7.5V, ELECTRI CAL VRMS =1.5V, IAC=100µA, ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=7.5V, no load on SS, CA Out, CHARACTERISTICS VA Out, REF, GT Drv, 55oC
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Multiplier Gain Constant OSCILLATOR Oscillator Frequency
CT Ramp Peak-to-Valley Amplitude CT Ramp Valley Voltage GATE DRIVER Maximum GT Drv Output Voltage 0mA load on GT Drv, 18V
46 86 4.9 0.8 13 12
62 118 5.9 1.3 18 1.5 2.2 0.4
PKLMT=0.1V PKLMT falling from 50mV to 50mV
Note 5: Multiplier Gain Constant (k) is defined by:
IMult Out =
k × IAC × (VA Out-1) VR MS2
Note 6: Guaranteed by design. Not 100% tested in production.
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PI N DESCRIPTIONS (Pin Numbers Refer to DIL Packages)
Gnd (Pin 1) (ground): All voltages are measured with respect to Gnd. VCC and REF should be bypassed directly to Gnd with an 0.1µF or larger ceramic capacitor. The timin g capacitor discharge current also returns to this pin, so the lead from the oscillator timing capacitor to Gnd should also be as short and as direct as possible. PKLMT (Pin 2) (peak limit): The threshold for PKLMT is 0.0V. Connect this input to the negative voltage on the current sense resistor as shown in Figure 1. Use a resistor to REF to offset the negative current sense signal up to Gnd. CA Out (Pin 3) (current amplifier output): This is the output of a wide-bandwidth op amp that senses line current and commands the pulse width modulator (PWM) to force the correct current. This output can swing close to Gnd, allowing the PWM to force zero duty cycle when necessary. The current amplifier will remain active even if the IC is disabled. The current amplifier output stage is an NPN emitter follower pull-up and an 8k resistor to ground. ISENSE (Pin 4) (current sense minus): This is the inverting in put to the current amplifier. This input and the non-inverting input Mult Out remain functional down to and belo w Gnd. Care should be taken to avoid taking these in puts below 0.5V, because they are protected with diodes to Gnd. Mult Out (Pin 5) (multiplier output and current sense plus): The output of the analog multiplier and the non-inverting input of the current amplifier are connected together at Mult Out. The cautions about taking ISENSE below 0.5V also apply to Mult Out. As the multiplier output is a current, this is a high impedance input similar to ISENSE, so the current amplifier can be configured as a diffe re ntial amplifier to reject Gnd noise. Figure 1 shows an example of using the current amplifier differentially. IAC (Pin 6) (input AC current): This input to the analog multip lier is a current. The multiplier is tailored for very lo w distortion from this current input (IAC) to Mult Out, so this is the only multiplier input that should be used for sensing instantaneous line voltage. The nominal voltage on IAC is 6V, so in addition to a resistor from IAC to rectified 60Hz, connect a resistor from IAC to REF. If the resistor to REF is one fourth of the value of the resistor to the rectifier, then the 6V offset will be cancelled, and the line current will have minimal cross-over distortion. VA Out (Pin 7) (voltage amplifier output): This is the output of the op amp that regulates output voltage. Like the current amplifier, the voltage amplifier will stay active even if the IC is disabled with either ENA or VCC. This means that large feedback capacitors across the amplifier will stay charged through momentary disable cycles. Voltage amplifier output levels below 1V will inhibit multiplier output. The voltage amplifier output is internally limited to approximately 5.8V to prevent overshoot. The voltage amplifier output stage is an NPN emitter follower pull-up and an 8k resistor to ground.
UC1854 UC28 54 UC38 54
VRMS (Pin 8) (RMS line voltage): The output of a boost PWM is proportional to the input voltage, so when the line volta ge into a low-bandwidth boost PWM voltage regulator changes, the output will change immediately and slowly recover to the regulated level. For these devices, the VRMS input compensates for line voltage changes if it is connected to a voltage proportional to the RMS input line voltage. For best control, the VRMS voltage should stay between 1.5V and 3.5V. RE F (Pin 9) (voltage reference output): REF is the output of an accurate 7.5V voltage reference. This output is capab le of delivering 10mA to peripheral circuitry and is internally short circuit current limited. REF is disabled and will remain at 0V when VCC is low or when ENA is low. Byp ass REF to Gnd with an 0.1µF or larger ceramic capacitor for best stability. ENA (Pin 10) (enable): ENA is a logic input that will enable the PWM output, voltage reference, and oscillator. ENA also will release the soft start clamp, allowing SS to rise. When unused, connect ENA to a +5V supply or pull ENA high with a 22k resistor. The ENA pin is not intended to be used as a high speed shutdown to the PWM output. VSENSE (Pin 11) (voltage amplifier inverting input): This is normally connected to a feedback network and to the boost converter output through a divider network. RSET (Pin 12) (oscillator charging current and multiplier limit set): A resistor from RSET to ground will program oscilla tor charging current and maximum multiplier output. Multiplier output current will not exceed 3.75V divided by the resistor from RSET to ground. SS (Pin 13) (soft start): SS will remain at Gnd as long as the IC is disabled or VCC is too low. SS will pull up to over 8V by an internal 14µA current source when both VCC becomes valid and the IC is enabled. SS will act as the reference input to the voltage amplifier if SS is below REF. With a large capacitor from SS to Gnd, the reference to the voltage regulating amplifier will rise slowly, and increase the PWM duty cycle slowly. In the event of a disable command or a supply dropout, SS will quickly discha rge to ground and disable the PWM. CT (Pin 14) (oscillator timing capacitor): A capacitor from CT to Gnd will set the PWM oscillator frequency according to this relationship:
F=
1.25 RSET × CT
VCC (Pin 15) (positive supply voltage): Connect VCC to a stable source of at least 20mA above 17V for normal operation. Also bypass VCC directly to Gnd to absorb supply current spikes required to charge external MOSFET gate capacitances. To prevent inadequate GT Drv signals, these devices will be inhibited unless VCC exceeds the upp er under-voltage lockout threshold and remains above the lower threshold.
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UC18 54 UC28 54 UC38 54 PI N DESCRIPTIONS (cont.)
GT Drv (Pin 16) (gate drive): The output of the PWM is a totem pole MOSFET gate driver on GT Drv. This output is in ternally clamped to 15V so that the IC can be operated with VCC as high as 35V. Use a series gate resistor of at le ast 5 ohms to prevent interaction between the gate imped ance and the GT Drv output driver that might cause the GT Drv output to overshoot excessively. Some overshoo t of the GT Drv output is always expected when driving a capacitive load.
TYPICAL CHARACTERISTICS at TA = TJ = 25°C
Current Amplifier Gain and Phase vs Frequency
120
V oltage Amplifier Gain and Phase vs Frequency
120
Phase Margin degrees
100 80 60
Phase Margin degrees
100 80 60
Open-Loop 20 Gain dB 0
-20 0.1 1 10 100 1000 10000
40
Open-Loop 40 20 Gain dB 0
-20 0.1 1 10 100 1000 10000
Frequency kHz
Frequency kHz
Gate Drive Rise and Fall Time
700 600 500 Fall Time Rise Time
Gate Drive Maximum Duty Cycle
100% 95% 90%
ns
400 300 200 100 0 0 0.01 0.02 0.03 0.04 0.05
Duty 85% Cycle
80% 75% 70%
1 10 100
Load Capacitance, µF
RSET, k
Mu ltiplier Output vs Voltage on Mult
600
Mult Out=3V Mult Out=2V
Oscillator Frequency vs RSET and CT
1000
500
Mult Out=1 Mult Out=0V
400
Multiplier Output 300 µA
200
Frequency kHz 100
VRMS=2V, VA Out=5V
100pF 200pF
500pF 1nF
100
10nF 5nF 3nF 2nF
0
0 100 200 300 400 500
10
600
700
800
1
10
100
IAC, µA
RSET, k
5
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