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Details, datasheet, quote on part number:5962-9450201QXA
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Datasheet text preview:
SN54ABT16646, SN74ABT16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS212D JUNE 1992 REVISED JULY 1999
D D D D D D D D
Members of the Texas Instruments WidebusTM Family State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JESD 17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (32-mA IOH, 64-mA IOL) Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54ABT16646 . . . WD PACKAGE SN74ABT16646 . . . DGG OR DL PACKAGE (TOP VIEW)
description
The 'ABT16646 devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 'ABT16646 devices.
1DIR 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2DIR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OE 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OE
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. The direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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SN54ABT16646, SN74ABT16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS212D JUNE 1992 REVISED JULY 1999
description (continued)
The SN54ABT16646 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT16646 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS OE X X H H L L L DIR X X X X L L H CLKAB X H or L X X X CLKBA X H or L X H or L X SAB X X X X X X L SBA X X X X L H X A1A8 Input Unspecified Input Input disabled Output Output Input DATA I/O B1B8 Unspecified Input Input Input disabled Input Input Output OPERATION OR FUNCTION OR FUNCTION Store A, B unspecified{ Store B, A unspecified{ Store A and B data Isolation, hold storage Real-time B data to A bus Stored B data to A bus Real-time A data to B Bus
L H H or L X H X Input Output Stored A data to bus The data-output functions can be enabled or disabled by various signals at OE or DIR. Data-input functions always are enabled, i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT16646, SN74ABT16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS212D JUNE 1992 REVISED JULY 1999
BUS B
OE L
DIR L
CLKAB CLKBA X X
SAB X
SBA L
OE L
DIR H
CLKAB X
CLKBA X
SAB L
BUS B SBA X REAL-TIME TRANSFER BUS A TO BUS B CLKAB X H or L CLKBA H or L X SAB X H BUS B SBA H X TRANSFER STORED DATA TO A AND/OR B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
BUS A
OE X X H
DIR X X X
CLKAB CLKBA X X
SAB X X X
SBA X X X
OE L L
STORAGE FROM A, B, OR A AND B
Figure 1. Bus-Management Functions
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
BUS A DIR L H
BUS A
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SN54ABT16646, SN74ABT16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS212D JUNE 1992 REVISED JULY 1999
logic symbol
1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB 56 1 55 54 2 3 29 28 30 31 27 26 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 C6 G7 G10 10 EN8 [BA] 10 EN9 [AB] C11 G12 C13 G14 1 1 6D 6 8 9 10 12 13 14 15 1 8 13D 14 16 17 19 20 21 23 24 1 14 12 11D 12 1 1 9 41 40 38 37 36 34 33 2B2 2B3 2B4 2B5 2B6 2B7 2B8 1 7 7 5 51 1 2 51 49 48 47 45 44 43 42 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 4D 52 1B1
1A1
5
1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1
2A2 2A3 2A4 2A5 2A6 2A7 2A8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT16646, SN74ABT16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS212D JUNE 1992 REVISED JULY 1999
logic diagram (positive logic)
1OE 56
1DIR 1CLKBA 1SBA 1CLKAB 1SAB
1 55 54 2 3
One of Eight Channels 1D C1 5 52 1D C1 1B1
1A1
2OE
29
To Seven Other Channels
2DIR 2CLKBA 2SBA 2CLKAB 2SAB
28 30 31 27 26
One of Eight Channels 1D C1 15 42 1D C1 2B1
2A1
To Seven Other Channels
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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