|
|
Part: 5962-9669801QXA
Category:
Logic
-> Transceivers
-> Registered Transceivers
Description: ti SN54ABTH18646A, Scan Test Devices With 18-Bit Transceivers And Registers
Company: Texas Instruments, Inc.
Datasheet: Download 5962-9669801QXA datasheet File size : 253 kB
Request For quote: Find where to buy 5962-9669801QXA
Datasheet text preview:
SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS166D AUGUST 1993 REVISED JULY 1996
D D D D D D D
Members of the Texas Instruments SCOPE TM Family of Testability Products Members of the Texas Instruments Widebus TM Family Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Include D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors B-Port Outputs of 'ABTH182646A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-B TM BiCMOS Design
D D
D
One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency SCOPE TM Instruction Set IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ Parallel-Signature Analysis at Inputs Pseudo-Random Pattern Generation From Outputs Sample Inputs/Toggle Outputs Binary Count From Outputs Device Identification Even-Parity Opcodes Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings
SN54ABTH18646A, SN54ABTH182646A . . . HV PACKAGE (TOP VIEW)
1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 NC VCC 2A1 2A2 2A3 GND 2A4 2A5 2A6
1A2 1A1 1OE GND 1SAB 1CLKAB TDO VCC NC TMS 1CLKBA 1SBA 1DIR GND 1B1 1B2 1B3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 87 6 5432 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
1B4 1B5 1B6 GND 1B7 1B8 1B9 VCC NC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7
2A7 2A8 2A9 GND 2OE 2SAB 2CLKAB TDI NC
NC No internal connection
VCC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE, Widebus, and EPIC-B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TCK 2CLKBA 2SBA GND 2DIR 2B9 2B8
Copyright © 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
1
SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS166D AUGUST 1993 REVISED JULY 1996
SN74ABTH18646A, SN74ABTH182646A . . . PM PACKAGE (TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 VCC 2A1 2A2 2A3 GND 2A4 2A5 2A6
1A 2 1A 1 1OE GND 1S A B 1 C LK A B TD O V CC TMS 1 C LK B A 1S B A 1DIR GND 1B 1 1B 2 1B 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1B4 1B5 1B6 GND 1B7 1B8 1B9 VCC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7
description
The 'ABTH18646A and 'ABTH182646A scan test devices with 18-bit bus transceivers and registers are members of the Texas Instruments SCOPE TM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed transmission of data directly from the input bus or from the internal registers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE TM bus transceivers and registers. Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating both buses. Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB and SAB, respectively. Figure 1 shows the four fundamental bus-management functions that are performed with the 'ABTH18646A and 'ABTH182646A.
2
2A7 2A8 2A9 GND 2OE 2SAB 2CLKAB TDI VCC TCK 2CLKBA 2SBA GND 2DIR 2B9 2B8
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS166D AUGUST 1993 REVISED JULY 1996
description (continued)
In the test mode, the normal operation of the SCOPE TM bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. Active bus-hold circuitry holds unused or floating data inputs at a valid logic level. The B-port outputs of 'ABTH182646A, which are designed to source or sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot. The SN54ABTH18646A and SN54ABTH182646A are characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABTH18646A and SN74ABTH182646A are characterized for operation from 40°C to 85°C.
FUNCTION TABLE (normal mode, each 9-bit section) INPUTS OE X X H H L L L DIR X X X X L L H CLKAB X L X X X CLKBA X L X X X SAB X X X X X X L SBA X X X X L H X A1 A9 Input Unspecified Input Input disabled Output Output Input DATA I/O B1 B9 Unspecified Input Input Input disabled Input Input disabled Output OPERATION OR FUNCTION OR FUNCTION Store A, B unspecified Store B, A unspecified Store A and B data Isolation, hold storage Real-time B data to A bus Stored B data to A bus Real-time A data to B bus
L H X X H X Input disabled Output Stored A data to B bus The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS166D AUGUST 1993 REVISED JULY 1996
BUS B
OE L
DIR L
CLKAB CLKBA X X
SAB X
SBA L
OE L
DIR H
CLKAB X
CLKBA X
SAB L
BUS B SBA X REAL-TIME TRANSFER BUS A TO BUS B CLKAB X X CLKBA X X SAB X H BUS B SBA H X TRANSFER STORED DATA TO A AND/OR B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
BUS A
OE X X H
DIR X X X
CLKAB CLKBA X X STORAGE FROM A, B, OR A AND B
SAB X X X
SBA X X X
OE L L
Figure 1. Bus-Management Functions
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
BUS A DIR L H
BUS A
SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS166D AUGUST 1993 REVISED JULY 1996
functional block diagram
1OE VCC 62 53 55 54 59 60
Boundary-Scan Register
1DIR 1CLKBA 1SBA 1CLKAB 1SAB
C1 1D
1A1
63
C1 1D One of Nine Channels
51
1B1
VCC 21 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB 30 27 28 23 22
C1 1D
2A1
10
C1 1D One of Nine Channels
40
2B1
Bypass Register
Boundary-Control Register Identification Register
VCC 24 TDI VCC 56 TMS 26 TCK Pin numbers shown are for the PM package.
58
Instruction Register
TDO
TAP Controller
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
Others parts begin by 59
59-1 59-2 59-3 59-4 59-5 59-6 59-7 59-8 59-9 59-10 59-11 59-12 59-13 59-14 59-15 59-16 59-17 59-18 59-19 59-20 59-21 59-22 59-23 59-24 59-25
|
|
|
