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Part: 5962-9674601QLA
Category:
Logic
-> Transceivers
-> Parity Transceivers
Description: ti SN54ABT853, 8-Bit to 9-Bit Parity Bus Transceivers
Company: Texas Instruments, Inc.
Datasheet: Download 5962-9674601QLA datasheet File size : 253 kB
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SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F FEBRUARY 1991 REVISED OCTOBER 1997
D D D D D D D D D
State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JESD 17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (32-mA IOH, 64-mA IOL) High-Impedance State During Power Up and Power Down Parity-Error Flag With Parity Generator/Checker Latch for Storage of Parity-Error Flag Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs
SN54ABT853 . . . JT OR W PACKAGE SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE (TOP VIEW)
OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB LE
SN54ABT853 . . . FK PACKAGE (TOP VIEW)
description
The 'ABT853 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT853 transceivers provide true data at their outputs.
A3 A4 A5 NC A6 A7 A8
5 6 7 8 9 10
A2 A1 OEA NC V CC B1 B2
4 3 2 1 28 27 26 25 24 23 22 21 20 11 19 12 13 14 15 16 17 18
B3 B4 B5 NC B6 B7 B8
NC No internal connection
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CLR GND NC LE OEB PARITY
ERR
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SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F FEBRUARY 1991 REVISED OCTOBER 1997
description (continued)
The SN54ABT853 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT853 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS OEB L H H X OEA H L L X CLR X X H L H H H L X X L L X LE X L H H H H L L X Ai OF H Odd Even NA NA X X X L Odd H Even Odd Even NA = not applicable, NC = no change, X = don't care Summation of high-level inputs includes PARITY along with Bi inputs. Output states shown assume ERR was previously high. § In this mode, ERR (when clocked) shows inverted parity of the A bus. NA NA A H L X Z Z Z Bi OF H NA Odd Even X X A NA B X X OUTPUTS AND I/Os B A NA NA NA PARITY L H NA NA NA ERR NA H L NC H NC H H L NA A data to B bus and generate inverted parity Isolation§ (parity check) FUNCTION A data to B bus and generate parity B data to A bus and check parity Store error flag Clear error flag register
logic symbol¶
LE CLR OEA OEB A1 A2 A3 A4 A5 A6 A7 A8 13 11 1 14 2 3 4 5 6 7 8 9 8 8
A Bus B Bus
LE CLR OEA OEB 1
ERR 10 ERR
PARITY 1
15 23 22 21 20 19 18 17 16
PARITY B1 B2 B3 B4 B5 B6 B7 B8
¶ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F FEBRUARY 1991 REVISED OCTOBER 1997
logic diagram (positive logic)
29 A1 A8 8 8x 8 EN 8x EN 14 OEB 8 2316 B1B8
1 OEA 8 8 MUX
15 PARITY
1 1 1 1 G1 13 LE 11 CLR
9
2k P
10
ERR
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. ERROR-FLAG FUNCTION TABLE INPUTS CLR L LE L INTERNAL TO DEVICE POINT P L H L H L H L H H X H X X OUTPUT PRESTATE ERRN1 X X L H X L H OUTPUT ERR L H L L H H L H Clear Store Sample FUNCTION
Pass
The state of ERR before changes at CLR, LE, or point P
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F FEBRUARY 1991 REVISED OCTOBER 1997
error-flag waveforms
H OEB L H OEA L
Even Bi + PARITY Odd
H LE L
H CLR L
H ERR Pass Store Clear Sample L
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F FEBRUARY 1991 REVISED OCTOBER 1997
recommended operating conditions (see Note 3)
SN54ABT853 MIN VCC VIH VIL VI VOH IOH IOL t/v t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate Outputs enabled 200 55 125 ERR Except ERR 0 4.5 2 0.8 VCC 5.5 24 48 10 200 40 85 0 MAX 5.5 SN74ABT853 MIN 4.5 2 0.8 VCC 5.5 32 64 10 MAX 5.5 UNIT V V V V V mA mA ns/V µs/V °C
TA Operating free-air temperature NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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