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Part: 5962-9674801QLA
Category:
Logic
-> Transceivers
-> Registered Transceivers
Description: ti SN54LVTH646, 3.3-V Abt Octal Bus Transceivers And Registers With 3-STATE Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 5962-9674801QLA datasheet File size : 253 kB
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Datasheet text preview:
SN54LVTH646, SN74LVTH646 3.3 V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3 STATE OUTPUTS
SCBS705G - AUGUST 1997 - REVISED OCTOBER 2003
D Support Mixed-Mode Signal Operation D D D
(5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion
D Bus Hold on Data Inputs Eliminates the D D
Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A)
SN54LVTH646 . . . FK PACKAGE (TOP VIEW)
12
13
NC - No internal connection
description/ordering information
These bus transceivers and registers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. ORDERING INFORMATION
TA SOIC - DW SOP - NS -40°C to 85 C 85°C SSOP - DB TSSOP - PW TVSOP - DGV CDIP - JT -55°C to 125 C 125°C CFP - W PACKAGE Tube Tape and reel Tape and reel Tape and reel Tube Tape and reel Tape and reel Tube Tube ORDERABLE PART NUMBER SN74LVTH646DW SN74LVTH646DWR SN74LVTH646NSR SN74LVTH646DBR SN74LVTH646PW SN74LVTH646PWR SN74LVTH646DGVR SNJ54LVTH646JT SNJ54LVTH646W LXH646 LXH646 SNJ54LVTH646JT SNJ54LVTH646W LVTH646 LVTH646 LXH646 TOP-SIDE MARKING
LCCC - FK Tube SNJ54LVTH646FK SNJ54LVTH646FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
A7 A8 GND NC B8 B7 B6
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
CLKAB SAB DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10 11
24 23 22 21 20 19 18 17 16 15 14
VCC CLKBA SBA OE B1 B2 B3 B4 B5 B6 B7 B8
A1 A2 A3 NC A4 A5 A6
DIR SAB C LK A B NC VCC C LK B A SBA
4 5 6 7 8 9 10 3 2 1 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18
SN54LVTH646 . . . JT OR W PACKAGE SN74LVTH646 . . . DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW)
OE B1 B2 NC B3 B4 B5
Copyright 2003, Texas Instruments Incorporated
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SCBS705G - AUGUST 1997 - REVISED OCTOBER 2003
SN54LVTH646, SN74LVTH646 3.3 V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3 STATE OUTPUTS
description/ordering information (continued)
The 'LVTH646 devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 'LVTH646. Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
FUNCTION TABLE INPUTS OE X X H H L L L DIR X X X X L L H CLKAB X H or L X X X CLKBA X H or L X H or L X SAB X X X X X X L SBA X X X X L H X A1-A8 Input Unspecified Input Input disabled Output Output Input DATA I/Os B1-B8 Unspecified Input Input Input disabled Input Input Output OPERATION OR FUNCTION Store A, B unspecified Store B, A unspecified Store A and B data Isolation, hold storage Real-time B data to A bus Stored B data to A bus Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LVTH646, SN74LVTH646 3.3 V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3 STATE OUTPUTS
SCBS705G - AUGUST 1997 - REVISED OCTOBER 2003
BUS B
21 OE L
3 DIR L
1 23 CLKAB CLKBA X X
2 SAB X
22 SBA L
21 OE L
3 DIR H
1 CLKAB X
23 CLKBA X
2 SAB L
BUS B 22 SBA X REAL-TIME TRANSFER BUS A TO BUS B 1 CLKAB X L 23 CLKBA L X 2 SAB X H BUS B 22 SBA H X TRANSFER STORED DATA TO A AND/OR B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
BUS A
21 OE X X H
3 DIR X X X
1 23 CLKAB CLKBA X X STORAGE FROM A, B, OR A AND B
2 SAB X X X
22 SBA X X X
21 OE L L
Pin numbers shown are for the DB, DGV, DW, JT, NS, PW, and W packages.
Figure 1. Bus-Management Functions
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
BUS A 3 DIR L H
BUS A
3
SCBS705G - AUGUST 1997 - REVISED OCTOBER 2003
SN54LVTH646, SN74LVTH646 3.3 V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3 STATE OUTPUTS
logic diagram (positive logic)
21 OE
3 DIR CLKBA SBA CLKAB 2 SAB 23 22 1
One of Eight Channels 1D C1
4 A1 1D C1 20 B1
To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, JT, NS, PW, and W packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LVTH646, SN74LVTH646 3.3 V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3 STATE OUTPUTS
SCBS705G - AUGUST 1997 - REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH646 . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTH646 . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54LVTH646 MIN VCC VIH VIL VI IOH IOL t /v t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate Outputs enabled 200 2.7 2 0.8 5.5 -24 48 10 200 MAX 3.6 SN74LVTH646 MIN 2.7 2 0.8 5.5 -32 64 10 MAX 3.6 UNIT V V V V mA mA ns/V µs/V
TA Operating free-air temperature -55 125 -40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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