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Part: 5962-9677201QXA
Category:
Interface and Interconnect
-> IEEE 1394 (Firewire)
-> Physical Layer Controllers
Description: ti TSB14C01, Single-port Backplane Physical Layer Transceiver
Company: Texas Instruments, Inc.
Datasheet: Download 5962-9677201QXA datasheet File size : 253 kB
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Datasheet text preview:
TSB14C01 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B ญ MARCH 1996 ญ REVISED MAY 1997
D D D D D D
Supports Provisions of IEEE 1394-1995 (1394) Standard for High-Performance Serial Bus Fully Interoperable With FireWireTM Implementation of 1394 Provides A Backplane Environment That Supports 50 or 100 Megabits per Second (Mbits/s) Logic Performs System Initialization and Arbitration Functions Encode and Decode Functions Included for Data-Strobe Bit-Level Encoding Incoming Data Resynchronized to Local Clock
D D D D D D
Separate Transmitter and Receiver for Greater Flexibility Data Interface to Link-Layer Controller (Link) Provided Through Two Parallel Signal Lines at 25/50 MHz 100-MHz or 50-MHz Oscillator Provides Transmit, Receive-Data, and Link Clocks at 25/50 MHz Single 5-V Supply Operation Packaged in a High-Performance 64-Pin TQFP (PM) Package for 0ฐC to 70ฐC Operation Packaged in a 68-Pin CFP (HV) Package for ญ 55ฐC to 125ฐC Operation
description
The TSB14C01 provides the transceiver functions needed to implement a single port node in a backplanebased 1394 network. The TSB14C01 provides two terminals for transmitting, two terminals for receiving, and a single terminal to externally control the drivers for data and strobe. The TSB14C01 is not designed to drive the backplane directly, this function must be provided externally. The TSB14C01 is designed to interface with a link-layer controller (link), such as the TSB12C01A. The TSB14C01 requires an external 98.304-MHz or 49.152-MHz reference oscillator input for S100/50 operation. The reference signal is internally divided to provide the 49.152-MHz ฑ100-ppm system clock signals used to control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is supplied to the associated link for synchronization of the two chips, when this device is in the S100 mode of operation, OSC_SEL is asserted high. When the TSB14C01 is in the S50 mode of operation, the clock rate supplied to the link is 24.576 MHz. Data bits to be transmitted are received from the link on two parallel paths and are latched internally in the TSB14C01 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and then transmitted at 98.304-Mbits/s (in S100 mode) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted on TDATA, and the encoded strobe information is transmitted on TSTRB. During packet reception the encoded information is received on RDATA and strobe information on RSTRB. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two parallel streams, resynchronized to the local system clock, and sent to the associated link. The TSB14C01 is a 5-V device and provides CMOS-level outputs.
AVAILABLE OPTIONS PACKAGES TA 0ฐC to 70ฐC ญ 55ฐC to 125ฐC CERAMIC FLAT PACK (HV) -- TSB14C01MHV THIN QUAD FLAT PACK (PM) TSB14C01PM --
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited. FireWire is a trademark of Apple Computer, Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright ฉ 1997, Texas Instruments Incorporated
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TSB14C01 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B ญ MARCH 1996 ญ REVISED MAY 1997
PM PACKAGE (TOP VIEW)
ARB_CLK PHYENA VC C ENA_PRI VC C N_POR GND LREQ VCC SCLK TSCLK GND CTL0 CTL1 D0 D1
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
OSC_SEL GND NC NC NC NC NC RDATA RSTRB VCC TDATA TSTRB GND N_OEB_D GND PTEST_INDRV VCC NC
10 11 12 13 14 15
33 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC ญ No connection
2
VCC EN_EXID EN_EXPRI EX_ID5 EX_ID4 EX_ID3 EX_ID2 EX_ID1 EX_ID0 GND EX_PRI3 EX_PRI2 EX_PRI1 EX_PRI0 NC NC
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GND RPREFIX VCC VCC GND VCC TI1 VCC NC XI_50 GND NC XI_100 GND
TSB14C01
ท DALLAS, TEXAS 75265
TSB14C01 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B ญ MARCH 1996 ญ REVISED MAY 1997
HV PACKAGE (TOP VIEW)
NC ARB_CLK PHYENA VCC ENA_PRI VC C N_POR GND LREQ VCC SCLK TSCLK GND CTL0 CTL1 D0 D1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
NC GND RPREFIX VCC VCC GND VCC TI1 VCC NC XI_50 GND NC XI_100 GND OSC_SEL GND
87 6 5432 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
TSB14C01M
52 51 50 49 48 47 46
45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC NC NC NC NC RDATA RSTRB VC C TDATA TSTRB GND N_OEB_D GND PTEST_INDRV VC C NC NC
NC ญ No connection
VCC EN_EXID EN_EXPRI EX_ID5 EX_ID4 EX_ID3 EX_ID2 EX_ID1 EX_ID0 GND EX_PRI3 EX_PRI2 EX_PRI1 EX_PRI0 NC
NC NC
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TSB14C01 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B ญ MARCH 1996 ญ REVISED MAY 1997
system block diagram
N_OEB_D D0 ญ D1 2
/
2
TSB14C01
Tdata Rdata Tstrb Rstrb
BPdata
Host Interface
1394 LinkLayer Controller
CTL0 ญ CTL1
/
LREQ
1394 Backplane PhysicalLayer Controller
BPstrb
SCLK
NOTE A: The backplane transceiver is customer supplied and is different for each type of backplane.
functional block diagram
SCLK D0, D1 Data Encode SCLK Physical ID Pr0 ญ Pr3 2 D0 ญ D1 CTL0 ญ CTL1 LREQ LINK/PHY Interface Fair/Urg Req Iso Req Cycle Req Ack Req Arb Won Arb Lost Arb Res Gap Sub Act Gap Ack Gap Bus Reset CLK (see Note A) CLK CLK RxStb RxData Data Resync/ Decode RSTRB RDATA ARB Control TxArbStrb TxArbData CLK TxPktStrb TxPktData ARB/DATA MUX TSTRB TDATA
/
2
/
RxData RxCLK RxCLK
NOTE A: CLK is either terminal XI_50 or XI_100 depending on the mode selection.
4
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TSB14C01 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B ญ MARCH 1996 ญ REVISED MAY 1997
Terminal Functions
TERMINAL NAME ARB_CLK PM NO. 1 HV NO. 11 TYPE TTL I/O O DESCRIPTION Arbitration clock. ARB_CLK is the clock used for arbitration. ARB_CLK is for test and debug. It can be put into a high-impedance state by PTEST_INDRV. This terminal is not used in normal operation and is always at 49.152 MHz.
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CTL0, CTL1 13, 14มมมม 23, 24 TTL I/O Control I/O. These are bidirectional signals that communicate between the TSB14C01 and the link that control passage of information between the two devices. Data I/O. These are bidirectional information signals that communicate between the TSB14C01 and the link. D0, D1 15, 16 4 25, 26 14 30 TTL TTL TTL I/O I I ENA_PRI Enable priority. ENA_PRI is tied low to enable the 7-bit bus request. See Table 1 for more information. EN_EXID 18 Enable external ID. When EN_EXID is asserted high, the ID for this node is set externally by EX_ID. When this terminal is tied/driven low, the source of the ID comes from the internal ID register. Enable external priority. When EN_EXPRI is asserted high (external priority enabled) the priority level for this node is set externally (see Table 1). This terminal should be tied low when not used. EN_EXPRI 19 31 TTL I EX_ID5 ญ EX_ID0 EX_PRI3 ญ EX_PRI0 GND 20,21,22, 23,24,25 27,28, 29,30 32,33,34, 35,36,37 39,40, 41,42 TTL TTL I I External ID. The ID for this node is determined by the value on the EX_ID terminals. Bit 0 is the MSB. External priority. The priority for this node is determined by the values on the EX_PRI terminals. See Table 1 for more information. Circuit ground 7,12,26, 36,38,49, 51,54,60, 64 8 4,8,17, 22,38,48, 50,61,63, 66 18 Supply -- LREQ VCC TTL I Link request input. LREQ is an input from the link used by the link to signal the TSB14C01 of a request to perform some service. Circuit power 3,5,9,17, 34,41,57, 59,61,62 1,3,5,6, 13,15,19, 29,46,53 Supply -- NC 31,32,33, 44,45,46, 47,48,53, 56 37 6 9,10,27, 28,43ญ45, 56ญ60, 65,68 49 16 62 -- -- Not connected. These terminals must be left floating. N_OEB_D N_POR TTL TTL O I I External driver enable. N_OEB_D is a negative active signal that enables the external driver for TDATA and TSTRB. Logic reset input . Forcing N_POR low causes a reset condition and resets the internal logic to the reset start state. OSC_SEL 50 VCC / GND TTL Select clock frequency. OSC_SEL should be pulled up to VCC when the operating frequency is 50 MHz. When the operating frequency is 100 MHz then it should be pulled to ground. It should not be left floating. PHYENA 2 12 O Phy enable. When the phy is driving it is low, PHYENA is the control to the CTL0, CTL1, D0, and D1 drivers. PHYENA is for test and debug. It can be put into a high-impedance state by PTEST_INDRV. This terminal is not used in normal operation. Test output enable. PTEST_INDRV enables/disables the drivers to the test terminals ARB_CLK, PHYENA, and RPREFIX. During normal operation, PTEST_INDRV should be tied to VCC to disable the drivers. Receive data. Incoming data is received at the data rate. PTEST_INDRV 35 47 TTL I RDATA 43 55 TTL I
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