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Part: 5962-9678001QXA
Category:
Logic
-> Transceivers
-> Standard Transceivers
Description: ti SN54LVTH162245, 3.3-V Abt 16-Bit Bus Transceivers With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 5962-9678001QXA datasheet File size : 253 kB
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Datasheet text preview:
SN54LVTH162245, SN74LVTH162245 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS260O JUNE 1993 REVISED SEPTEMBER 2003
D D D D D D D D D D D
Members of the Texas Instruments Widebus Family A-Port Outputs Have Equivalent 22- Series Resistors, So No External Resistors Are Required Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
SN54LVTH162245 . . . WD PACKAGE SN74LVTH162245 . . . DGG OR DL PACKAGE (TOP VIEW)
1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE
description/ordering information
The 'LVTH162245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. ORDERING INFORMATION
TA SSOP DL 85°C 40°C to 85 C TSSOP DGG VFBGA GQL VFBGA ZQL (Pb-free) PACKAGE Tube Tape and reel Tape and reel Tape and reel ORDERABLE PART NUMBER SN74LVTH162245DL SN74LVTH162245DLR SN74LVTH162245DGGR SN74LVTH162245KR 74LVTH162245ZQLR TOP-SIDE MARKING LVTH162245 LVTH162245 LL2245
55°C to 125°C CFP WD Tube SNJ54LVTH162245WD SNJ54LVTH162245WD Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN54LVTH162245, SN74LVTH162245 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS260O JUNE 1993 REVISED SEPTEMBER 2003
description/ordering information (continued)
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 22- series resistors to reduce overshoot and undershoot. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
GQL OR ZQL PACKAGE (TOP VIEW) 1 A B C D E F G H J K 2 3 4 5 6
terminal assignments
1 A B C D E F G H J K 1DIR 1B2 1B4 1B6 1B8 2B1 2B3 2B5 2B7 2DIR 2 NC 1B1 1B3 1B5 1B7 2B2 2B4 2B6 2B8 NC GND VCC GND NC GND VCC GND NC 3 NC GND VCC GND 4 NC GND VCC GND 5 NC 1A1 1A3 1A5 1A7 2A2 2A4 2A6 2A8 NC 6 1OE 1A2 1A4 1A6 1A8 2A1 2A3 2A5 2A7 2OE
NC No internal connection FUNCTION TABLE (each 8-bit section) INPUTS OE L L H DIR L H X OPERATION B data to A bus A data to B bus Isolation
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LVTH162245, SN74LVTH162245 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS260O JUNE 1993 REVISED SEPTEMBER 2003
logic diagram (positive logic)
1DIR 1 2DIR 48 24
1OE
25
2OE
1A1
47
2A1
36
2
1B1
13
2B1
To Seven Other Channels Pin numbers shown are for the DGG, DL, and WD packages.
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH162245 (B port) . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH162245 (B port) . . . . . . . . . . . . . . . . . . . . . . . . 128 mA A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Current into any output in the high state, IO (see Note 2): SN54LVTH162245 (B port) . . . . . . . . . . . . . 48 mA SN74LVTH162245 (B port) . . . . . . . . . . . . . 64 mA A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN54LVTH162245, SN74LVTH162245 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS260O JUNE 1993 REVISED SEPTEMBER 2003
recommended operating conditions (see Note 4)
SN54LVTH162245 MIN VCC VIH VIL VI IOH IOL t/v t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate A port B port A port B port Outputs enabled 200 2.7 2 0.8 5.5 12 24 12 48 10 200 MAX 3.6 SN74LVTH162245 MIN 2.7 2 0.8 5.5 12 32 12 64 10 MAX 3.6 UNIT V V V V mA mA ns/V µs/V
TA Operating free-air temperature 55 125 40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LVTH162245, SN74LVTH162245 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS260O JUNE 1993 REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK A port VOH B port TEST CONDITIONS VCC = 2.7 V, VCC = 2.7 V to 3.6 V, VCC = 3 V, VCC = 2.7 V to 3.6 V, VCC = 2.7 V, VCC = 3 V A port VCC = 2.7 V to 3.6 V, VCC = 3 V, VCC = 2.7 V VOL B port VCC = 3 V II = 18 mA IOH = 100 µA IOH = 12 mA IOH = 100 µA IOH = 8 mA IOH = 24 mA IOH = 32 mA IOL = 100 µA IOL = 12 mA IOL = 100 µA IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 48 mA IOL = 64 mA VI = VCC or GND VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V ±100* ±100* 0.19 5 0.19 0.3 4 10 4 10 75 75 MIN SN54LVTH162245 TYP MAX 1.2 VCC0.2 2 VCC0.2 2.4 2 2 0.2 0.8 0.2 0.5 0.4 0.5 0.55 0.55 ±1 10 20 5 10 75 75 500 750 ±100 ±100 0.19 5 0.19 0.2 mA pF pF mA µA ±1 10 20 5 10 ±100 µA µA 0.2 0.8 0.2 0.5 0.4 0.5 V VCC0.2 2 VCC0.2 2.4 V MIN SN74LVTH162245 TYP MAX 1.2 UNIT V
Control inputs II A or B ports
VCC = 3.6 V, VCC = 0 or 3.6 V, VCC = 3.6 V VCC = 0, VCC = 3 V
Ioff
II(hold)
A or B ports VCC = 3.6 V§,
IOZPU IOZPD
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high Outputs low Outputs disabled
µA µA
ICC
ICC¶ Ci Cio
VCC = 3 V to 3.6 V, One input at VCC 0.6 V, Other inputs at VCC or GND VI = 3 V or 0 VO = 3 V or 0
* On products compliant to MIL-PRF-38535, this parameter is not production tested. All typical values are at VCC = 3.3 V, TA = 25°C. Unused pins at VCC or GND. § This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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