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Part: 5962-9689001QXA
Category:
Logic
-> Backplane Logic (GTL, GTLP, FB/FB+, ABTE/ETL)
Description: ti SN54GTL16612, 18-Bit Gtl/lvt Universal Bus Transceivers
Company: Texas Instruments, Inc.
Datasheet: Download 5962-9689001QXA datasheet File size : 279 kB
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Datasheet text preview:
SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K JUNE 1994 REVISED AUGUST 2001
D D D D D D D D D D
Members of Texas Instruments' Widebus Family UBT Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Translate Between GTL/GTL+ Signal Levels and LVTTL Logic Levels Support Mixed-Mode (3.3 V and 5 V) Signal Operation on A-Port and Control Inputs Identical to '16601 Function Ioff Supports Partial-Power-Down Mode Operation Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 500 mA Per JESD 17
SN54GTL16612 . . . WD PACKAGE SN74GTL16612 . . . DGG OR DL PACKAGE (TOP VIEW)
description
The 'GTL16612 devices are 18-bit UBT transceivers that provide LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for transparent, latched, clocked, and clock-enabled modes of data transfer identical to the '16601 function. The devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC circuitry.
OEAB LEAB A1 GND A2 A3 VCC (3.3 V) A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC (3.3 V) A16 A17 GND A18 OEBA LEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
CEAB CLKAB B1 GND B2 B3 VCC (5 V) B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VREF B16 B17 GND B18 CLKBA CEBA
The user has the flexibility of using these devices at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. VCC (5 V) supplies the internal and GTL circuitry while VCC (3.3 V) supplies the LVTTL output buffers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OEC, UBT, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K JUNE 1994 REVISED AUGUST 2001
description (continued)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable(LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that for A to B, but uses OEBA, LEBA, CLKBA, and CEBA. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. ORDERING INFORMATION
TA PACKAGE SSOP DL DL TSSOP DGG Tube Tape and reel Tape and reel ORDERABLE PART NUMBER SN74GTL16612DL SN74GTL16612DLR SN74GTL16612DGGR TOP-SIDE MARKING GTL16612 GTL16612
40°C to 85°C
55°C to 125°C CFP WD Tube SNJ54GTL16612WD SNJ54GTL16612WD Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS CEAB X L L X X L L OEAB H L L L L L L LEAB X L L H H L L CLKAB X H L X X A X X X L H L H OUTPUT B Z B0§ B0¶ L H L H B0¶ MODE Isolation Latched storage of A data storage of data Transparent Clocked storage of A data storage of data
H L L X X Clock inhibit A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. § Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low ¶ Output level before the indicated steady-state input conditions were established
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K JUNE 1994 REVISED AUGUST 2001
logic diagram (positive logic)
35 VREF 1 OEAB CEAB 56
55 CLKAB 2 LEAB 28 LEBA 30 CLKBA CEBA 29
27 OEBA 3 A1 CE 1D C1 CLK CE 1D C1 CLK 54
B1
To 17 Other Channels
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K JUNE 1994 REVISED AUGUST 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC: 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V B port and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Voltage range applied to any output in the high or power-off state, VO (see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V Current into any output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 mA Current into any A-port output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Notes 4 through 7)
SN54GTL16612 MIN VCC VTT VREF VI VIH VIL IIK IOH IOL Supply voltage voltage Termination voltage Reference voltage voltage Input voltage voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current A port A port B port 3.3 V 5V GTL GTL+ GTL GTL+ B port Except B port B port Except B port B port Except B port VREF+50 mV 2 VREF50 mV 0.8 18 32 64 40 3.15 4.75 1.14 1.35 0.74 0.87 NOM 3.3 5 1.2 1.5 0.8 1 MAX 3.45 5.25 1.26 1.65 0.87 1.1 VTT 5.5 VREF+50 mV 2 VREF50 mV 0.8 18 32 64 40 MIN 3.15 4.75 1.14 1.35 0.74 0.87 SN74GTL16612 NOM 3.3 5 1.2 1.5 0.8 1 MAX 3.45 5.25 1.26 1.65 0.87 1.1 VTT 5.5 UNIT V V V V V V mA mA mA
TA Operating free-air temperature 55 125 40 85 °C NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5. Normal connection sequence is GND first, VCC = 5 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. 6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. 7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K JUNE 1994 REVISED AUGUST 2001
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK TEST CONDITIONS CONDITIONS VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V VCC (3.3 V)= 3.15 V to 3.45 V, VCC (5 V) = 4.75 V to 5.25 V VCC ( (3.3 V) = 3.15 V, , VCC (5 V) = 4.75 V II = 18 mA IOH = 100 µA IOH = 8 mA IOH = 32 mA IOL = 100 µA IOL = 16 mA IOL = 32 mA IOL = 64 mA VCC (3.3 V)0.2 2.4 2 0.2 0.4 0.5 0.6 0.5 10 1000 1 30 5 5 1000 75 75 ±500 1 10 1 10 1 5 1 120 120 120 1 75 75 ±500 1 10 1 10 1 5 1 120 120 120 1 mA mA mA µA µA µA SN54GTL16612 MIN TYP MAX 1.2 VCC (3.3 V)0.2 2.4 2 0.2 0.4 0.5 0.55 0.4 10 20 1 30 5 5 100 µA µA V V SN74GTL16612 MIN TYP MAX 1.2 UNIT V
VOH
A port t
VOL
A port port
VCC ( (3.3 V) = 3.15 V, , VCC (5 V) = 4.75 V
B port Control inputs
VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V, IOL = 40 mA VCC (3.3 V) = 0 or 3.45 V, VI = 5.5 V VCC (5 V) = 0 or 5.25 V VCC (3 3 V) = 3 45 V, (3.3 3.45 V VCC (5 V) = 5.25 V (5 V) 5 25 VCC ( (3.3 V) = 3.45 V, , VCC (5 V) = 5.25 V VCC = 0, VI = 5.5 V VI = VCC (3.3 V) VI = 0 VI = VCC (3.3 V) VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V
II
A port
B port port Ioff II(hold) A port A port B port A port B port A or B port
VCC (3 3 V) = 3 15 V, (3.3 3.15 V VCC (5 V) = 4.75 V (5 V) 4 75
IOZH IOZL ICC (3.3 V)
VI = 0 to VCC (3.3 V) VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 3 V VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 1.2 V VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.5 V VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.4 V Outputs high VCC (3.3 V) = 3.45 V, (3.3 3.45 V, Outputs low VCC (5 V) = 5.25 V, IO = 0, VI = VCC (3.3 V) or GND Outputs disabled VCC (3.3 V) = 3.45 V, (3.3 3.45 V, VCC (5 V) = 5.25 V, IO = 0, VI = VCC (3.3 V) or GND Outputs high Outputs low Outputs disabled
ICC V) (5 V)
A or B port
ICC§ Ci Cio Control inputs A port B port
VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, A-port or control inputs at VCC (3.3 V) or GND, One input at 2.7 V VI = 3.15 V or 0 VO = 3 15 V or 0 3.15 or 3.5 12
12 18 10
3.5 12 5
pF pF
All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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