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Part: 5962-9689401Q2A
Category:
Data Conversion
-> ADC (Analog to Digital Converters)
Description: ti TLV1543, 10-Bit 200 KSPS ADC Ser. Out, Built-in Self-test Modes, Inherent S&H, Pin Compat. W/TLC1543, 11 Ch.
Company: Texas Instruments, Inc.
Datasheet: Download 5962-9689401Q2A datasheet File size : 279 kB
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TLV1543C, TLV1543I, TLV1543M 3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072D DECEMBER 1992 REVISED JULY 2000
D D D D D D D D D D
3.3-V Supply Operation 10-Bit-Resolution A/D Converter 11 Analog Input Channels Three Built-In Self-Test Modes Inherent Sample and Hold Total Unadjusted Error . . . ± 1 LSB Max On-Chip System Clock End-of-Conversion (EOC) Output Pin Compatible With TLC1543 CMOS Technology
DB, DW, FK, J, OR N PACKAGE (TOP VIEW)
A0 A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC EOC I/O CLOCK ADDRESS DATA OUT CS REF + REF A10 A9
description
The TLV1543C, TLV1543I, and TLV1543M are CMOS 10-bit, switched-capacitor, successiveapproximation, analog-to-digital converters. These devices have three inputs and a 3-state output [chip select (CS), input-output clock (I/O CLOCK), address input (ADDRESS), and data output (DATA OUT)] that provide a direct 4-wire interface to the serial port of a host processor. The devices allow high-speed data transfers from the host.
FN PACKAGE (TOP VIEW)
A3 A4 A5 A6 A7
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
A2 A1 A0 VCC EOC I/O CLOCK ADDRESS DATA OUT CS REF +
PACKAGE
In addition to a high-speed A /D converter and versatile control capability, these devices have an on-chip 14-channel multiplexer that can select any one of 11 analog inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic. At the end of A /D conversion, the end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated in the devices features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating free-air temperature range. The TLV1543C is characterized for operation from 0°C to 70°C. The TLV1543I is characterized for industrial temperature range of 40°C to 85°C. The TLV1543M is characterized for operation over the full military temperature range of 55°C to 125°C.
AVAILABLE OPTIONS SMALL OUTLINE (DB) TLV1543CDB TLV1543IDB -- SMALL OUTLINE (DW) TLV1543CDW -- -- PLASTIC CHIP CARRIER (FN) TLV1543CFN -- --
TA 0°C to 70°C 40°C to 85°C 55°C to 125°C
CHIP CARRIER (FK) -- -- TLV1543MFK
CERAMIC DIP (J) -- -- TLV1543MJ
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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· DALLAS, TEXAS 75265
A8 GND A9 A10 REF
-- --
PLASTIC DIP (N) TLV1543CN
1
TLV1543C, TLV1543I, TLV1543M 3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072D DECEMBER 1992 REVISED JULY 2000
functional block diagram
REF + 14 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 1 2 3 4 5 6 7 8 9 11 12 Sample and Hold REF 13
10-Bit Analog-to-Digital Converter (switched capacitors) 10
14-Channel Analog Multiplexer
4
Input Address Register
Output Data Register
10
10-to-1 Data Selector and Driver
16
DATA OUT
4 3 Self-Test Reference ADDRESS 17 System Clock, Control Logic, and I/O Counters
19
EOC
I/O CLOCK CS
18 15
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE 1 k TYP A0 A10 Ci = 60 pF TYP (equivalent input capacitance) A0 A10 5 M TYP INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLV1543C, TLV1543I, TLV1543M 3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072D DECEMBER 1992 REVISED JULY 2000
Terminal Functions
TERMINAL NAME ADDRESS NO. 17 I/O I DESCRIPTION Serial address. A 4-bit serial address selects the desired analog input or test voltage that is to be converted next. The address data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK. After the four address bits have been read into the address register, ADDRESS is ignored for the remainder of the current conversion period. Analog signal. The 11 analog inputs are applied to A0 A10 and are internally multiplexed. The driving source impedance should be less than or equal to 1 k. Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT, ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup time plus two falling edges of the internal system clock. The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS is high and active when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next most significant bit, and the remaining bits are shifted out in order with the LSB appearing on the ninth falling edge of I/O CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial interface data transfers of more than ten clocks produce zeroes as the unused LSBs. End of conversion. EOC goes from a high- to a low- logic level on the trailing edge of the tenth I/O CLOCK and remains low until the conversion is complete and data are ready for transfer. The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. Input/output clock. I/O CLOCK receives the serial I/O CLOCK input and performs the following four functions: 1) It clocks the four input address bits into the address register on the first four rising edges of I/O CLOCK with the multiplex address available after the fourth rising edge. 2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins charging the capacitor array and continues to do so until the tenth falling edge of I/O CLOCK. 3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT. 4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock. The upper reference voltage value (nominally VCC) is applied to REF +. The maximum input voltage range is determined by the difference between the voltage applied to REF + and the voltage applied to the REF terminal. The lower reference voltage value (nominally ground) is applied to REF . Positive supply voltage
A0 A10 CS
1 9, 11, 12 15
I I
DATA OUT
16
O
EOC GND I/O CLOCK
19 10 18
O I I
REF +
14
I
REF VCC
13 20
I I
detailed description
With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state. The host then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O CLOCK. During this transfer, the host serial interface also receives the previous conversion result from DATA OUT. I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host. The first four I/O clocks load the address register with the 4-bit address on ADDRESS selecting the desired analog channel and the next six clocks providing the control timing for sampling the analog input.
POST OFFICE BOX 655303
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3
TLV1543C, TLV1543I, TLV1543M 3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072D DECEMBER 1992 REVISED JULY 2000
detailed description (continued)
There are six basic serial interface timing modes that can be used with the device. These modes are determined by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode with a 10-clock transfer and CS inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, (4) a fast mode with a 16-bit transfer and CS active (low) continuously, (5) a slow mode with an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, and (6) a slow mode with a 16-clock transfer and CS active (low) continuously. The MSB of the previous conversion appears on DATA OUT on the falling edge of CS in mode 1, mode 3, and mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the 16th clock falling edge in mode 6. The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data are transmitted to the host through DATA OUT. The number of serial clock pulses used also depends on the mode of operation, but a minimum of ten clock pulses is required for conversion to begin. On the 10th clock falling edge, the EOC output goes low and returns to the high logic level when conversion is complete and the result can be read by the host. On the 10th clock falling edge, the internal logic takes DATA OUT low to ensure that the remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long. Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that can be used, and the timing edge on which the MSB of the previous conversion appears at the output. Table 1. Mode Operation
MODES Mode 1 Fast Modes Modes Mode 2 Mode 3 Mode 4 Slow Modes Modes Mode 5 Mode 6 CS High between conversion cycles Low continuously High between conversion cycles Low continuously High between conversion cycles Low continuously NO. OF I/O CLOCKS 10 10 11 to 16 16 11 to 16 16 MSB AT DATA OUT CS falling edge EOC rising edge CS falling edge EOC rising edge CS falling edge 16th clock falling edge TIMING DIAGRAM Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14
These edges also initiate serial-interface communication. No more than 16 clocks should be used.
fast modes The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not begin until the falling edge of the 10th I/O CLOCK.
mode 1: fast mode, CS inactive (high) between conversion cycles, 10-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling edges of the internal system clock.
mode 2: fast mode, CS active (low) continuously, 10-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous conversion to appear immediately on this output.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLV1543C, TLV1543I, TLV1543M 3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072D DECEMBER 1992 REVISED JULY 2000
mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling edges of the internal system clock. mode 4: fast mode, CS active (low) continuously, 16-clock transfer In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous conversion to appear immediately on this output.
slow modes In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must occur before the conversion period is complete; otherwise, the device loses synchronization with the host serial interface, and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must occur within 9.5 µs after the tenth I/O clock falling edge.
mode 5: slow mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling edges of the internal system clock. mode 6: slow mode, CS active (low) continuously, 16-clock transfer In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next 16-clock transfer initiated by the serial interface.
address bits The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal (MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address selects one of 14 inputs (11 analog inputs or 3 internal test inputs). analog inputs and test modes The 11 analog inputs and the 3 internal test inputs are selected by the 14-channel multiplexer according to the input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching. Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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