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Part: 5962-9760401QDA

Category:
 Logic
   -> Gates
     -> NOR Gates

Description: ti SN54LVC02A, Quadruple 2-INPUT Positive-nOR GATEs

Company: Texas Instruments, Inc.

Datasheet: Download 5962-9760401QDA datasheet     File size : 311 kB

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Datasheet text preview:
SN54LVC02A, SN74LVC02A QUADRUPLE 2 INPUT POSITIVE NOR GATES
SCAS280O - JANUARY 1993 - REVISED JULY 2003

D D D D D

Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.4 ns at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C

D Latch-Up Performance Exceeds 250 mA Per D
JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101)

VCC

1A 1Y NC VCC
3 4 5 6 7 8

SN54LVC02A . . . J OR W PACKAGE SN74LVC02A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW)

SN74LVC02A . . . RGY PACKAGE (TOP VIEW)

SN54LVC02A . . . FK PACKAGE (TOP VIEW)

1Y 1A 1B 2Y 2A 2B GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

VCC 4Y 4B 4A 3Y 3B 3A

1

1Y

14 13 4Y 12 4B 11 4A 10 3Y 9 3B

1A 1B 2Y 2A 2B

2 3 4 5 6 7 8

1B NC 2Y NC 2A

2 1 20 19 18 17 16 15

4Y 4B NC 4A NC 3Y

14 9 10 11 12 13

GND

description/ordering information

NC - No internal connection

The SN54LVC02A quadruple 2-input positive-NOR gate is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC02A quadruple 2-input positive-NOR gate is designed for 1.65-V to 3.6-V VCC operation. The 'LVC02A devices perform the Boolean function Y = A + B or Y = A · B in positive logic. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. ORDERING INFORMATION
TA PACKAGE QFN - RGY Reel of 1000 Tube of 50 SOIC - D -40°C to 85 C 85°C SOP - NS SSOP - DB Reel of 2500 Reel of 250 Reel of 2000 Reel of 2000 Tube of 90 TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W LCCC - FK Reel of 2000 Reel of of 250 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74LVC02ARGYR SN74LVC02AD SN74LVC02ADR SN74LVC02ADT SN74LVC02ANSR SN74LVC02ADBR SN74LVC02APW SN74LVC02APWR SN74LVC02APWT SNJ54LVC02AJ SNJ54LVC02AW SNJ54LVC02AFK SNJ54LVC02AJ SNJ54LVC02AW SNJ54LVC02AFK LC02A LVC02A LC02A LVC02A TOP-SIDE MARKING LC02A

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

Copyright 2003, Texas Instruments Incorporated

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· DALLAS, TEXAS 75265

2B GND NC 3A 3B

3A

1

SN54LVC02A, SN74LVC02A QUADRUPLE 2 INPUT POSITIVE NOR GATES
SCAS280O - JANUARY 1993 - REVISED JULY 2003

FUNCTION TABLE (each gate) INPUTS A H X L B X H L OUTPUT Y L L H

logic diagram, each gate (positive logic)
A B Y

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply-voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input-voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Output-voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5.

2

POST OFFICE BOX 655303

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SN54LVC02A, SN74LVC02A QUADRUPLE 2 INPUT POSITIVE NOR GATES
SCAS280O - JANUARY 1993 - REVISED JULY 2003

recommended operating conditions (see Note 5)
SN54LVC02A MIN Operating VCC Supply voltage Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 12 24 -12 -24 2 1.5 MAX 3.6 SN74LVC02A MIN 1.65 1.5 0.65 × VCC 1.7 2 2 0.35 × VCC 0.7 0.8 5.5 VCC 0 0 0.8 5.5 VCC -4 -8 -12 -24 4 8 12 24 mA mA V V V V MAX 3.6 V UNIT

VIH

High-level input voltage

VIL VI VO

Low-level input voltage Input voltage Output voltage

IOH

High-level output current

IOL

Low-level output current

TA Operating free-air temperature -55 125 -40 85 °C NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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3

SN54LVC02A, SN74LVC02A QUADRUPLE 2 INPUT POSITIVE NOR GATES
SCAS280O - JANUARY 1993 - REVISED JULY 2003

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -100 µA A IOH = -4 mA IOH = -8 mA IOH = -12 mA IOH = -24 mA IOL = 100 µA A VOL IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA II ICC ICC VI = 5.5 V or GND VI = VCC or GND, IO = 0 One input at VCC - 0.6 V, Other inputs at VCC or GND VCC 1.65 V to 3.6 V 2.7 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 2.7 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3.6 V 3.6 V 2.7 V to 3.6 V 3.3 V 5 0.4 0.55 ±5 10 500 5 0.2 0.45 0.7 0.4 0.55 ±5 10 500 µA µA µA pF V 2.2 2.4 2.2 VCC-0.2 1.2 1.7 2.2 2.4 2.2 0.2 V MIN SN54LVC02A TYP MAX MIN SN74LVC02A TYP MAX UNIT

VCC-0.2

VOH

Ci VI = VCC or GND All typical values are at VCC = 3.3 V, TA = 25°C.

switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVC02A PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 2.7 V MIN tpd A or B Y MAX 5.4 VCC = 3.3 V ± 0.3 V MIN 1 MAX 4.4 ns UNIT

switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC02A PARAMETER FROM (INPUT) A or B TO (OUTPUT) Y VCC = 1.8 V ± 0.15 V MIN tpd tsk(o) 1 MAX 8.9 VCC = 2.5 V ± 0.2 V MIN 1 MAX 7.4 VCC = 2.7 V MIN 1 MAX 5.4 VCC = 3.3 V ± 0.3 V MIN 1 MAX 4.4 1 ns ns UNIT

operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per gate TEST CONDITIONS f = 10 MHz VCC = 1.8 V TYP 7.5 VCC = 2.5 V TYP 8.5 VCC = 3.3 V TYP 9.5 UNIT pF

4

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SN54LVC02A, SN74LVC02A QUADRUPLE 2 INPUT POSITIVE NOR GATES
SCAS280O - JANUARY 1993 - REVISED JULY 2003

PARAMETER MEASUREMENT INFORMATION
S1 VLOAD Open GND RL TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open VLOAD GND

From Output Under Test CL (see Note A)

RL

LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI VCC VCC 2.7 V 2.7 V tr/tf 2 ns 2 ns 2.5 ns 2.5 ns VM VCC/2 VCC/2 1.5 V 1.5 V VLOAD 2 × VCC 2 × VCC 6V 6V CL 30 pF 30 pF 50 pF 50 pF RL 1 k 500 500 500 V 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input tw VI Input VM VM 0V VOLTAGE WAVEFORMS PULSE DURATION VI Input tPLH Output tPHL VM VM VM VM 0V tPHL VOH VM VOL tPLH VOH Output VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) Output Control tPZL VM tPZH VM VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM VM 0V tPLZ VLOAD/2 VOL + V tPHZ VOH - V VOH 0 V VOL Data Input tsu VM th VI VM 0V VM 0V

Output Waveform 1 S1 at VLOAD (see Note B)

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

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