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Part: 5HC40103F3AS228
Category:
Logic
-> Counters
-> Binary Counters
Description: ti CD54HC40103, High Speed CMOS Logic 8-Stage Synchronous Down Counters
Company: Texas Instruments, Inc.
Datasheet: Download 5HC40103F3AS228 datasheet File size : 153 kB
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Datasheet text preview:
CD54HC40103, CD74HC40103, CD74HCT40103
Data sheet acquired from Harris Semiconductor SCHS221D
November 1997 - Revised October 2003
High-Speed CMOS Logic 8-Stage Synchronous Down Counters
Description
The 'HC40103 and CD74HCT40103 are manufactured with high speed silicon gate technology and consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The 40103 contains a single 8-bit binar y counter. Each has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the TC output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK (CP). Counting is inhibited when the TE input is high. The TC output goes low when the count reaches zero if the TE input is low, and remains low for one full clock period. When the PE input is low, data at the P0-P7 inputs are clocked into the counter on the next positive clock transition regardless of the state of the TE input. When the PL input is low, data at the P0-P7 inputs are asynchronously forced into the counter regardless of the state of the PE, TE, or CLOCK inputs. Input P0-P7 represent a single 8-bit binar y word for the 40103. When the MR input is low, the counter is asynchronously cleared to its maximum count of 25510, regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table. If all control inputs except TE are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 10016 or 25610 clock pulses long. The 40103 may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode. These circuits possess the low power consumption usually associated with CMOS circuitr y, yet have speeds comparable to low power Schottky TTL circuits and can drive up to 10 LSTTL loads.
Features
· Synchronous or Asynchronous Preset
[ /Title (CD74H C40103, CD74H CT4010 3) /Subject (High Speed CMOS Logic 8-
· Cascadable in Synchronous or Ripple Mode · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC40103F3A CD74HC40103E CD74HC40103M CD74HC40103MT CD74HC40103M96 CD74HCT40103E CD74HCT40103M CD74HCT40103MT CD74HCT40103M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD54HC40103, CD74HC40103, CD74HCT40103 Pinout
CD54HC40103 (CERDIP) CD74HC40103, CD74HCT40103 (PDIP, SOIC) TOP VIEW
CP 1 MR 2 TE 3 P0 4 P1 5 P2 6 P3 7 GND 8
16 VCC 15 PE (SYNC) 14 TC 13 P7 12 P6 11 P5 10 P4 9 PL (ASYNC)
Functional Diagram
14 TC 13 12 11 10 7 6 5 4 GND 8 MR VCC TE CP 3 1 PE 15 PL 9 P7 P6 P5 P4 P3 P2 P1 P0
2
16
TRUTH TABLE CONTROL INPUTS MR 1 1 1 1 0 PL 1 1 1 0 X PE 1 1 0 X X TE 1 0 X X X Asynchronously PRESET MODE Synchronous Inhibit Counter Count Down Preset On Next Positive Clock Transition Preset Asychronously Clear to Maximum Count ACTION
1 = High Level. 0 = Low Level. X = Don't Care. Clock connected to clock input. Synchronous Operation: changes occur on negative-to-positive clock transitions. Load Inputs: MSB = P7, LSB = P0.
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CD54HC40103, CD74HC40103, CD74HCT40103
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
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CD54HC40103, CD74HC40103, CD74HCT40103
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT P0-P7 TE, MR CP PE PL UNIT LOADS (NOTE) 0.20 0.40 0.60 0.80 1.35
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC.
Prerequisite for Switching Specifications
25oC PARAMETER HC TYPES CP Pulse Width tW 2 4.5 6 PL Pulse Width tW 2 4.5 6 165 33 28 125 25 21 205 41 35 155 31 26 250 50 43 190 38 32 ns ns ns ns ns ns SYMBOL VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54HC40103, CD74HC40103, CD74HCT40103
Prerequisite for Switching Specifications
PARAMETER MR Pulse Width SYMBOL tW VCC (V) 2 4.5 6 CP Max. Frequency (Note 3) fCP(MAX) 2 4.5 6 P to CP Set-up Time tSU 2 4.5 6 PE to CP Set-up Time tSU 2 4.5 6 TE to CP Set-up Time tSU 2 4.5 6 P to CP Hold Time tH 2 4.5 6 TE to CP Hold Time tH 2 4.5 6 MR to CP Removal Time tREM 2 4.5 6 PE to CP Hold Time tH 2 4.5 6 HCT TYPES CP Pulse Width PL Pulse Width MR Pulse Width CP Max. Frequency (Note 3) P to CP Set-up Time PE to CP Set-up Time TE to CP Set-up Time P to CP Hold Time TE to CP Hold Time MR to CP Removal Time PE to CP Hold Time tW tW tW fCP(MAX) tSU tSU tSU tH tH tREM tH 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 35 43 35 14 24 20 40 5 0 10 2 44 54 44 11 30 25 50 5 0 13 2 53 65 53 9 36 30 60 5 0 15 2 ns ns ns MHz ns ns ns ns ns ns ns (Continued) 25oC MIN 125 25 21 3 15 18 100 20 17 75 15 13 150 30 26 5 5 5 0 0 0 50 10 9 2 2 2 TYP MAX -40oC TO 85oC MIN 135 31 26 2 12 14 125 25 21 95 19 16 190 38 33 5 5 5 0 0 0 65 13 11 2 2 2 MAX -55oC TO 125oC MIN 190 38 32 2 10 12 150 30 26 110 22 19 225 45 38 5 5 5 0 0 0 75 15 13 2 2 2 MAX UNITS ns ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
5
Others parts begin by 5h
5H-1
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