|Category||Semiconductors => Logic => Gate => OR Gate|
|Part family||74AC11032 Quadruple 2-Input Positive-OR Gates|
|Description||Quadruple 2-Input Positive-OR Gates 16-SOIC -40 to 85|
|Company||Texas Instruments, Inc.|
|Datasheet||Download 74AC11032D datasheet
|Cross ref.||Similar parts: 74AC11032D-T|
|Output Drive (IOL/IOH)(Max)(mA)||24/-24|
|ICC @ Nom Voltage(Max)(mA)||0.04|
|Operating Temperature Range(C)||-40 to 85|
|tpd @ Nom Voltage(Max)(ns)||9.7,6.7|
|Approx. Price (US$)||0.94 | 1ku|
|F @ Nom Voltage(Max)(Mhz)||100|
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|• Input and Output Characteristics of Digital Integrated Circuits
This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding | Doc
|• TI IBIS File Creation, Validation, and Distribution Processes
The Input/Output Buffer Information Specification (IBIS), also known as ANSI/EIA-656, has become widely accepted among electronic design automation (EDA) vendors, semiconductor vendors, and system designers as the format for digital electrical interface da | Doc
|• Live Insertion
Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must always remain operational even during module maintenance | Doc
|• Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | Doc|
|• Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV, as generated by an IEC ESD simulator to determine the level of ISD protection provi | Doc
|• Designing With Logic (Rev. C)
Data sheets, which usually give information on device behavior only under recommended operating conditions, may only partially answer engineering questions that arise during the development of systems using logic devices. However, information is frequently | Doc
|• Introduction to Logic | Doc|
|• Implications of Slow or Floating CMOS Inputs (Rev. D) | Doc|
|• CMOS Power Consumption and CPD Calculation (Rev. B)
Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result, CMOS devices are best known for low power consumpti | Doc
|• Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
Though low power consumption is a feature of CMOS devices, sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This docu | Doc
Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N)description
This device contains four independent 2-input OR gates. It performs the Boolean function Y
FUNCTION TABLE (each gate) INPUTS OUTPUT
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC. 7 V Input voltage range, VI (see Note V to VCC 0.5 V Output voltage range, VO (see Note V to VCC 0.5 V Input clamp current, IIK (VI VI > VCC). ±20 mA Output clamp current, IOK (VO VO > VCC). ±50 mA Continuous output current, IO (VO 0 to VCC). ±50 mA Continuous current through VCC or GND. ±100 mA Maximum power dissipation = 55°C (in still air) (see Note 2): D package. W DB package. W N package. 1.1 W Storage temperature range, Tstg. to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.
MIN VCC VIH Supply voltage High-level input voltage VCC 3 V VCC 4.5 V VCC 5.5 V VCC 3 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC 3 V VCC 4.5 V VCC 5.5 V VCC 3 V IOL t/v TA Low-level output current Input transition rise or fall rate Operating free-air temperature VCC 4.5 V VCC 0 40 VCC 4.5 V VCC 5.5 V VCC ns/V °C mA NOM 5 MAX 5.5 UNIT V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VI = VCC or GND 5V 3.5 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
|Related products with the same datasheet|
|Some Part number from the same manufacture Texas Instruments, Inc.|
|74AC11032DB Quadruple 2-input Positive-OR GATE|
|74AC11032DBLE ti 74AC11032, Quadruple 2-Input Positive-OR GATEs|
|74AC11034 Hex Noninverter|
|74AC11034DW ti 74AC11034, Hex Noninverting Drivers|
|74AC11074 Dual D-type Positive Edge Triggered Flip-flop With Clear|
|74AC11074D ti 74AC11074, Dual Positive-edge-triggered D-type Flip-flops With Clear And Preset|
|74AC11074PW Dual Positive-edge-triggered D-type Flip-flop With Clear And Preset|
|74AC11074PWLE ti 74AC11074, Dual Positive-edge-triggered D-type Flip-flops With Clear And Preset|
|74AC11086 Quad 2-input Exclusive OR GATE|
|74AC11086D ti 74AC11086, Quadruple 2-Input Exclusive-OR GATEs|
|74AC11109 Dual J-k Positive-edge-triggered Flip-flop With Clear And Preset|
|74AC11109D ti 74AC11109, Dual J-k Positive-edge-triggered Flip-flops With Clear And Preset|
|74AC11112 Dual J-k Negative-edge-triggered Flip-flop With Clear And Preset|
|74AC11112D ti 74AC11112, Dual J-k Negative-edge-triggered Flip-flops With Clear And Preset|
|74AC11132 Quadruple 2-input Positive-nand Schmitt-trigger|
|74AC11132D ti 74AC11132, Quadruple 2-Input Positive-nand Gates With Schmitt-triggers|
|74AC11138 3-line to 8-line Inverting Decoder/demultiplexer|
|74AC11138D ti 74AC11138, 3-Line to 8-Line Decoders/demultiplexers|
|74AC11139 Dual 2-line Decoder/demultiplexer|
|74AC11139D ti 74AC11139, Dual 2-Line to 4-Line Decoders/demultiplexers|
|74AC11139PW Dual 2-line Decoder/demultiplexer|
CD4518BF3A : ti CD4518B, CMOS Dual BCD Up-counter
SN74LVC1G79YEPR : Single Gates ti SN74LVC1G79, Single Positive-edge-triggered D-type Flip-flop
SNJ54AHCT02FK : ti SN54AHCT02, Quadruple 2-Input Positive-nOR GATEs
TPS1100YPW : Single P-channel Enhancement-mode MOSFETs
TPS2830DR : MOSFET and Power Drivers ti TPS2830, Non-inverting Fast Synchronous Buck MOSFET Drivers With Enable
TL2575HV-12IKV : The TL2575 and TL2575HV greatly simplify the design of switching power supplies by conveniently providing all the active functions needed for a step-down (buck) switching regulator in an integrated circuit. Accepting a wide input voltage range of up to 60 V (HV version) and available in fixed output
TMS320VC5504 : Low-Power Fixed-Point Digital Signal Processor The TMS320VC5504 is a member of TI\'s TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications. The TMS320VC5504 fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core.
TLC071IDG4 : Family OF Wide-bandwidth High-output-drive Single Supply Operational Amplifiers
ULQ2004ATDQ1 : High-voltage High-crrent Darlington Transistor Array
TPS3106E12DVB : Ultralow Supply-current/supply-voltage Supervisory Circuits
ADS1672EVM-PDK : Eval Board - Analog To Digital Converter (adcs) Programmers, Development System; KIT DEMO FOR ADS1672 Specifications: Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
54F823FM : 9-bit D-type Flip-flop. The a 9-bit buffered register It Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems The 'F823 is functionally and pin compatible with AMD's Am29823 TRI-STATE outputs Clock Enable and Clear Direct replacement for AMD's Am29823 Package (0 300 Wide) Molded Dual-In-Line (0 300 Wide) Ceramic Dual-In-Line.
74F2643PCQR : Octal Bus Transceiver With 25 Series Resistors in The Output.
74LCXZ2245 : CMOS/BiCMOS->LVT/ALVT/LCX/LPT Family->Low Voltage. Low Voltage Bidriectional Transceiver With 5V Tolerant Inputs And Outputs And 26 Ohm Series Resistors in B Outputs.
CD74AC158 : Multiplexers->CMOS/BiCMOS->AC/ACT Family. Quad 2-input Multiplexers.
I74F04N : Hex Inverter. FEATURE TYPE TYPICAL PROPAGATION DELAY 3.5ns TYPICAL SUPPLY CURRENT ( TOTAL) 6.9mA ORDER CODE 14-pin plastic DIP 14-pin plastic SO COMMERCIAL RANGE VCC 5V ±10%, Tamb N74F04N N74F04D INDUSTRIAL RANGE VCC 5V ±10%, Tamb I74F04N I74F04D PKG DWG SOT27-1 SOT108-1 PINS nA Data inputs 74F (U.L.) HIGH/LOW 1.0/1.0 LOAD VALUE HIGH/LOW 20µA/0.6mA 1.0mA/20mA nY Data.
IDT29FCT2052AT : Bus Oriented Circuits. Fast CMOS Octal Registered Transceiver. A, B, and C grades Low input and output leakage 1µA (max.) CMOS power levels True TTL input and output compatibility: VOH = 3.3V (typ.) VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 s Power off disable outputs permit "live insertion" Available in SOIC and QSOP packages The an 8-bit registered transceiver.
IN74ACT258D : Quad 2-1 Data Selector/Multiplexer, Inv (3-State) 16. The IN74ACT258 is identical in pinout to the LS/ALS258, HC/HCT258. The IN74ACT258 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device selects a (4-bit) nibble from either the or B inputs as determined by the Select input. The nibble is presented at the outputs in inverted from when the Output Enable.
MC54HC32AJ : Quad 2-input OR GATE. The MC54/74HC32A is identical in pinout to the LS32. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: to 6V Low Input Current: 1µA High Noise Immunity Characteristic.
MM74HC174 : CMOS/BiCMOS->HC/HCT Family. Hex D-type Flip-flop With Clear. The MM74HC174 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 6 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup.
SN54LS641J : Octal Bus Transceivers. These octal bus transceivers are designed for asynchronous two-way communication between data buses. Control function implementation minimizes external timing requirements. These circuits allow data transmission from the A bus B or from the B bus to A bus depending upon the logic level of the direction control (DIR) input. Enable input (G) can disable.
SN74ALVC16374 : CMOS/BiCMOS->LVC/ALVC/VCX Family->Low Voltage. 16-bit Edge-triggered D-type Flip-flop With 3-state Outputs.
SN74F623 : Bus Oriented Circuits. Octal Bus Transceiver With 3-state Outputs. Local Bus-Latch Capability Noninverting Logic Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs These octal bus transceivers are designed for asynchronous communication between data buses. The control function implementation allows for maximum flexibility in timing. These devices.
SN74S20 : Bipolar->S Family. Dual 4-input NAND Gate.
TC74HC299 : CMOS/BiCMOS->HC/HCT Family. 8-bit Pipo Shift Register With Asnychronous Clear.
TC74HC4024AP : TC74HC Series. Function = 7-stage Binary Counter ;; Pins = 14.
M54HC4511F1R : HC/UH SERIES, SEVEN SEGMENT DECODER/DRIVER, TRUE OUTPUT, CDIP16. s: Function: Decoder ; Output Lines: 7-Segment ; Supply Voltage: 5V ; Package Type: DIP, CERAMIC, DIP-16 ; Logic Family: CMOS ; Number of Pins: 16 ; Propagation Delay: 77 ns ; Operating Temperature: -55 to 125 C (-67 to 257 F).
TC74AC08F(TP2) : AC SERIES, QUAD 2-INPUT AND GATE, PDSO14. s: Gate Type: AND ; Supply Voltage: 5V ; Logic Family: CMOS ; Inputs: 2 ; Propagation Delay: 8 ns ; Operating Temperature: -40 to 85 C (-40 to 185 F) ; Pin Count: 14 ; IC Package Type: SOIC, Other, 0.300 INCH, PLASTIC, SOIC-14.