Details, datasheet, quote on part number: 74AC11074
CategorySemiconductors => Logic => Flip-Flop/Latch/Register => D-Type Flip-Flop
Part family74AC11074 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
DescriptionDual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 85
CompanyTexas Instruments, Inc.
DatasheetDownload 74AC11074 datasheet
Cross ref.Similar parts: TC74AC74FN, TC74AC74FN-ELP, TC74AC74FT, TC74AC74FT(EL), TC74AC74P, TC74AC74P(F), CD74AC74E, CD74AC74M, CD74AC74EX, CD74AC74M96
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3-State OutputNo
Output Drive (IOL/IOH)(Max)(mA)24/-24
ICC @ Nom Voltage(Max)(mA)0.04
Operating Temperature Range(C)-40 to 85
Approx. Price (US$)0.71 | 1ku
Schmitt TriggerNo
F @ Nom Voltage(Max)(Mhz)100
Technology FamilyAC
tpd @ Nom Voltage(Max)(ns)11.4,8.2
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
14DSOICR-PDSO-G50TUBEAC11074 3.918.651.581.27
Application notes
• Input and Output Characteristics of Digital Integrated Circuits
This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding | Doc
• Power-Up Behavior of Clocked Devices (Rev. A) | Doc
• TI IBIS File Creation, Validation, and Distribution Processes
The Input/Output Buffer Information Specification (IBIS), also known as ANSI/EIA-656, has become widely accepted among electronic design automation (EDA) vendors, semiconductor vendors, and system designers as the format for digital electrical interface da | Doc
• Live Insertion
Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must always remain operational even during module maintenance | Doc
• Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | Doc
• Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV, as generated by an IEC ESD simulator to determine the level of ISD protection provi | Doc
• Designing With Logic (Rev. C)
Data sheets, which usually give information on device behavior only under recommended operating conditions, may only partially answer engineering questions that arise during the development of systems using logic devices. However, information is frequently | Doc
• Introduction to Logic | Doc
• Implications of Slow or Floating CMOS Inputs (Rev. D) | Doc
• CMOS Power Consumption and CPD Calculation (Rev. B)
Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result, CMOS devices are best known for low power consumpti | Doc
• Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
Though low power consumption is a feature of CMOS devices, sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This docu | Doc


Features, Applications

Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-m Process 500-mA Typical Latch-Up Immunity at 125C Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)


This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs. The 74AC11074 is characterized for operation from to 85C.

Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC. 7 V Input voltage range, VI (see Note V to VCC 0.5 V Output voltage range, VO (see Note V to VCC 0.5 V Input clamp current, IIK (VI VI > VCC). 20 mA Output clamp current, IOK (VO VO > VCC). 50 mA Continuous output current, IO (VO 0 to VCC). 50 mA Continuous current through VCC or GND. 100 mA Maximum power dissipation = 55C (in still air) (see Note 2): D package. W N package. W PW package. 0.5 W Storage temperature range, Tstg. to 150C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.

MIN VCC VIH Supply voltage High-level input voltage VCC 3 V VCC 4.5 V VCC 5.5 V VCC 3 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC 3 V VCC 4.5 V VCC 5.5 V IOL t/v TA Low-level output current Input transition rise or fall rate Operating free-air temperature VCC 3 V VCC 4.5 V VCC 0 40 VCC 4.5 V VCC 5.5 V VCC ns/V C mA NOM 5 MAX 5.5 UNIT V

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.


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0-C     D-L     M-R     S-Z