|Category||Semiconductors => Logic => Flip-Flop/Latch/Register => D-Type Flip-Flop|
|Part family||74AC11074 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset|
|Description||Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 85|
|Company||Texas Instruments, Inc.|
|Datasheet||Download 74AC11074 datasheet
|Cross ref.||Similar parts: TC74AC74FN, TC74AC74FN-ELP, TC74AC74FT, TC74AC74FT(EL), TC74AC74P, TC74AC74P(F), CD74AC74E, CD74AC74M, CD74AC74EX, CD74AC74M96|
|Output Drive (IOL/IOH)(Max)(mA)||24/-24|
|ICC @ Nom Voltage(Max)(mA)||0.04|
|Operating Temperature Range(C)||-40 to 85|
|Approx. Price (US$)||0.71 | 1ku|
|F @ Nom Voltage(Max)(Mhz)||100|
|tpd @ Nom Voltage(Max)(ns)||11.4,8.2|
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
|• Input and Output Characteristics of Digital Integrated Circuits
This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding | Doc
|• Power-Up Behavior of Clocked Devices (Rev. A) | Doc|
|• TI IBIS File Creation, Validation, and Distribution Processes
The Input/Output Buffer Information Specification (IBIS), also known as ANSI/EIA-656, has become widely accepted among electronic design automation (EDA) vendors, semiconductor vendors, and system designers as the format for digital electrical interface da | Doc
|• Live Insertion
Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must always remain operational even during module maintenance | Doc
|• Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | Doc|
|• Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV, as generated by an IEC ESD simulator to determine the level of ISD protection provi | Doc
|• Designing With Logic (Rev. C)
Data sheets, which usually give information on device behavior only under recommended operating conditions, may only partially answer engineering questions that arise during the development of systems using logic devices. However, information is frequently | Doc
|• Introduction to Logic | Doc|
|• Implications of Slow or Floating CMOS Inputs (Rev. D) | Doc|
|• CMOS Power Consumption and CPD Calculation (Rev. B)
Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result, CMOS devices are best known for low power consumpti | Doc
|• Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
Though low power consumption is a feature of CMOS devices, sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This docu | Doc
|74AC11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)description
This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs. The 74AC11074 is characterized for operation from to 85°C.
Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC. 7 V Input voltage range, VI (see Note V to VCC 0.5 V Output voltage range, VO (see Note V to VCC 0.5 V Input clamp current, IIK (VI VI > VCC). ±20 mA Output clamp current, IOK (VO VO > VCC). ±50 mA Continuous output current, IO (VO 0 to VCC). ±50 mA Continuous current through VCC or GND. 100 mA Maximum power dissipation = 55°C (in still air) (see Note 2): D package. W N package. W PW package. 0.5 W Storage temperature range, Tstg. to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.
MIN VCC VIH Supply voltage High-level input voltage VCC 3 V VCC 4.5 V VCC 5.5 V VCC 3 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC 3 V VCC 4.5 V VCC 5.5 V IOL t/v TA Low-level output current Input transition rise or fall rate Operating free-air temperature VCC 3 V VCC 4.5 V VCC 0 40 VCC 4.5 V VCC 5.5 V VCC ns/V °C mA NOM 5 MAX 5.5 UNIT V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
|Some Part number from the same manufacture Texas Instruments, Inc.|
|74AC11074D ti 74AC11074, Dual Positive-edge-triggered D-type Flip-flops With Clear And Preset|
|74AC11074PW Dual Positive-edge-triggered D-type Flip-flop With Clear And Preset|
|74AC11074PWLE ti 74AC11074, Dual Positive-edge-triggered D-type Flip-flops With Clear And Preset|
|74AC11086 Quad 2-input Exclusive OR GATE|
|74AC11086D ti 74AC11086, Quadruple 2-Input Exclusive-OR GATEs|
|74AC11109 Dual J-k Positive-edge-triggered Flip-flop With Clear And Preset|
|74AC11109D ti 74AC11109, Dual J-k Positive-edge-triggered Flip-flops With Clear And Preset|
|74AC11112 Dual J-k Negative-edge-triggered Flip-flop With Clear And Preset|
|74AC11112D ti 74AC11112, Dual J-k Negative-edge-triggered Flip-flops With Clear And Preset|
|74AC11132 Quadruple 2-input Positive-nand Schmitt-trigger|
|74AC11132D ti 74AC11132, Quadruple 2-Input Positive-nand Gates With Schmitt-triggers|
|74AC11138 3-line to 8-line Inverting Decoder/demultiplexer|
|74AC11138D ti 74AC11138, 3-Line to 8-Line Decoders/demultiplexers|
|74AC11139 Dual 2-line Decoder/demultiplexer|
|74AC11139D ti 74AC11139, Dual 2-Line to 4-Line Decoders/demultiplexers|
|74AC11139PW Dual 2-line Decoder/demultiplexer|
|74AC11139PWLE ti 74AC11139, Dual 2-Line to 4-Line Decoders/demultiplexers|
|74AC11151 1-of-8 Data Selector/multiplexer|
|74AC11151D ti 74AC11151, 1-Of-8 Data Selectors/multiplexers|
|74AC11153 Dual 1-of-4 Data Selector/multiplexer|
|74AC11153D ti 74AC11153, Dual 1-Of-4 Data Selectors/multiplexers|
SN74CBT3383DWR : Bus Exchange/Multiplexing Switches ti SN74CBT3383, 10-Bit Fet Bus-exchange Switches
SN74LVC1G132DCKR : Single 2-Input NAND Gate With Schmitt-trigger Input
TMX320C6202GLS : Fixed-point Digital Signal Processor
UC3704J : MOSFET and Power Drivers ti UC3704, Bridge Transducer Switch
UCC2913 : Power Negative Voltage Hot Swap Power Manager
TPS54060DGQR : 3.5V To 60V Input, 0.5A, 2.5MHz Step Down SWIFT™ Converter With Eco-Mode™ The TPS54060 device is a 60V, 0.5A, step down regulator with an integrated high side MOSFET. Current mode control provides simple external compensation and flexible component selection. A low ripple pulse skip mode reduces th
74ALVCH16373DGGRG4 : 1-bit TO 2-bit Address Driver WITH 3-state Outputs
ADS830E/2K5G4 : Data Acquisition - Analog To Digital Converter (adc) Integrated Circuit (ics) 2 Single-Ended, Unipolar; 1 Differential, Unipolar Tape & Reel (TR) Single Supply; IC 8BIT 60MHZ ADC CONV 20-QSOP Specifications: Number of Bits: 8 ; Package / Case: 20-SSOP (0.154", 3.90mm Width) ; Data Interface: Parallel ; Packaging: Tape & Reel (TR) ; Sampling Rate (Per Second): 60M ; Operating Temperature: -40°C ~ 85°C ; Voltage Supply Source: Single Supply ; Number of Inputs and Type: 2 Single-Ended,
TMS320C6414CGLZ6E3 : Fixed/floating-point DSP
XILINXPWR-083 : Eval Board - Dc/dc & Ac/dc (off-line) Smp Programmers, Development System; EVAL MODULE FOR XILINX FPGA Specifications: Board Type: Fully Populated ; Main Purpose: DC/DC, Step Down with LDO ; Regulator Topology: Buck ; Outputs and Type: 3, Non-Isolated ; Voltage - Output: 1.2V, 3.3V, 2.5V ; Current - Output: 1.5A, 1.5A, 250mA ; Voltage - Input: 5V ; Frequency - Switching: - ; Power - Output: - ; Utili
TMDSVDP64X : Obsolete/discontinued Part Number Programmers, Development System; VIDEOPHONE DEVELOPMENT PLATFORM Specifications: Type: DSP ; Contents: - ; For Use With/Related Products: TMS320DM64x ; Lead Free Status: Contains Lead ; RoHS Status: RoHS Non-Compliant
74LVTH16835 : CMOS/BiCMOS->LVT/ALVT/LCX/LPT Family->Low Voltage. Low Voltage 18-Bit Universal Bus Driver With 3-STATE Outputs.
DG201ACK : Quad SPST CMOS Analog Switches.
HD74ALVC1G125 : . Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips.
HD75159 : Line Drivers. Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips.
IDT74ALVC162830 : Bus Oriented Circuits. 3.3v CMOS 1-bit to 2-bit Address Driver With 3-state Outputs.
IDT74FCT162827ET : Fast CMOS 20-bit Buffers. Common : 0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) 250ps Low input and output leakage 1µ A (max.) ESD > 2000V per MIL-STD-883, Method > 200V using machine model 0) Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack.
M74HC692 : HC/HCT->High Speed CMOS. Decade Counter/register (3-STATE). HIGH SPEED: fMAX = 53 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) for to QD OUTPUT |IOH| = IOL = 4mA (MIN) for RCO OUTPUT BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) to 6V PIN AND FUNCTION COMPATIBLE.
MB2543 : MB2543; Dual Octal Latched Transceivers With Dual Enable (3-State);; Package: SOT379-2 (QFP52).
MC10106FN : Triple 4-3-3-input NOR GATE. L SUFFIX CERAMIC PACKAGE CASE 62010 P SUFFIX PLASTIC PACKAGE CASE 64808 Pin assignment is for DualinLine Package. For PLCC pin assignment, see the Pin Conversion Tables on page 611 of the Motorola MECL Data Book (DL122/D). Characteristic Power Supply Drain Current Input Current Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching.
MM82C19 : CMOS/BiCMOS->4000 Family. 16-Line to 1-Line Multiplexer. The MM74C150 and MM82C19 multiplex 16 digital lines to 1 output. A 4-bit address code determines the particular 1of-16 inputs which is routed to the output. The data is inverted from input to output. A strobe override places the output MM74C150 in the logical "1" state and the output MM82C19 in the highimpedance state. All inputs are protected from.
PI74ST1G00 : 2-Input NAND Gate. High-speed: tPD = 1.8ns typical Broad operating range: VCC 1.8V 3.6V Power down high-impedance inputs/outputs High output drive: at 3V VCC Package: 5-pin space saving SOT23 and SC70 The a 2-input NAND gate that operates over the to 3.6V VCC operating range. Pericoms PI74ST series of products are produced using the Companys advanced submicron technology.
SN74ALS1003A : Bipolar->ALS Family. Quadruple 2-input Positive-nand Buffers With Open-collector Outputs.
SN74ALS845-1NT : D-Type (3-State) Latches. ti SN74ALS845, 8-Bit Bus-interface D-type Latches With 3-State Outputs.
SN74F520DW : Identity Comparators. ti SN74F520, Octal Binary And BCD Identity Comparators With Enable.
TC74HC279 : CMOS/BiCMOS->HC/HCT Family. Quad S-r Latch.
A32300DXRQG208C : FPGA, 3749 CLBS, 30000 GATES, PQFP208. s: System Gates: 30000 ; Logic Cells / Logic Blocks: 3749 ; Package Type: QFP, Other, POWER, PLASTIC, QFP-208 ; Logic Family: CMOS ; Pins: 208 ; Operating Temperature: 0 to 70 C (32 to 158 F) ; Supply Voltage: 5V.
74AC253CW : AC SERIES, DUAL 4 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, UUC16. s: Output Characteristics: 3-State, TRUE ; Logic Family: CMOS ; Number of Pins: 16 ; Inputs: 4 ; Propagation Delay: 16 ns.
74HC4094D/T3 : HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16. s: Register Type: Serial In / Parallel Out ; Shift Direction: Right ; Supply Voltage: 5V ; Output Characteristics: 3-State ; Package Type: Other, MINI, PLASTIC, SO-16 ; Logic Family: CMOS ; Pin Count: 16 ; Number of units in IC: 1 ; Number of Bits (Stages): 8 ; Clock.
935210570118 : LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16. s: Counter Type: BINARY COUNTER ; Counter Category: Synchronous ; Counter Direction: Bidirectional ; Supply Voltage: 1.2V, 3.6V, 2.7 ; Package Type: 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SO-16 ; Logic Family: CMOS, LVC/LCX/Z ; Number of Pins: 16 ; Number of Stages.