Details, datasheet, quote on part number: 74AC11112D
CategoryLogic => Flip-Flops
Descriptionti 74AC11112, Dual J-k Negative-edge-triggered Flip-flops With Clear And Preset
CompanyTexas Instruments, Inc.
DatasheetDownload 74AC11112D datasheet
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Features, Applications

Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C ESD Protection Exceeds 2000 V, MIL STD-883C Method 3015 Package Options Include Plastic SmallOutline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs


These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

­ No internal connection FUNCTION TABLE (each gate) INPUTS PRE CLR CLK OUTPUTS H L Toggle H{ QO This configuration is nonstable; that is, it will not persist when either PRE or CLR returns to its inactive (high) level.

The 54AC11112 is characterized for operation over the full military temperature range to 125°C. The 74AC11112 is characterized for operation from to 85°C.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.

logic diagram, each flip-flop (positive logic)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC. 7 V Input voltage range, VI (see Note V to VCC 0.5 V Output voltage range, VO (see Note V to VCC 0.5 V Input clamp current, IIK (VI VI > VCC). 20 mA Output clamp current, IOK (VO VO > VCC). 50 mA Continuous output current, IO (VO 0 to VCC). 50 mA Continuous current through VCC or GND. 100 mA Storage temperature range. to 150°C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

54AC11112 MIN VCC VIH Supply voltage High-level input voltage VCC 3 V VCC 4.5 V VCC 5.5 V VCC 3 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC 3 V VCC 4.5 V VCC 5.5 V VCC 3 V IOL /v TA Low-level output current Input transition rise or fall rate Operating free-air temperature VCC 4.5 V VCC ­ 55 VCC 4.5 V VCC 5.5 V VCC NOM 5 MAX 5.5 74AC11112 MIN VCC ns/ °C mA NOM 5 MAX 5.5 UNIT V

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VI = VCC or GND 5V 3.5 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.


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