|Category||Semiconductors => Switches and Multiplexers => Buffered Encoders and Decoders|
|Part family||74AC11138 3-Line to 8-Line Decoders/Demultiplexers|
|Description||3-Line to 8-Line Decoders/Demultiplexers 16-SOIC -40 to 85|
|Company||Texas Instruments, Inc.|
|Datasheet||Download 74AC11138D datasheet
|Cross ref.||Similar parts: 74AC11138D-T, CD4028B, CD4511B, CD4543B, CD4555B, CD4556B, CD74AC138, CD74AC139, CD74AC238|
|Output Drive (IOL/IOH)(Max)(mA)||24/-24|
|ICC @ Nom Voltage(Max)(mA)||0.04|
|Operating Temperature Range(C)||-40 to 85|
|tpd @ Nom Voltage(Max)(ns)||12.2,8.8|
|F @ Nom Voltage(Max)(Mhz)||100|
|ESD Charged Device Model(kV)||0.75|
|Approx. Price (US$)||1.00 | 1ku|
|Digital input leakage(Max)(uA)||5|
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
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Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)description
The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select (A, B, C) inputs and the three enable G2A, G2B) inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The 74AC11138 is characterized for operation from to 85°C.FUNCTION TABLE ENABLE INPUTS G2A G2B SELECT INPUTS Y1 Y2 OUTPUTS Y6 Y7
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC. 7 V Input voltage range, VI (see Note V to VCC 0.5 V Output voltage range, VO (see Note V to VCC 0.5 V Input clamp current, IIK (VI VI > VCC). ±20 mA Output clamp current, IOK (VO VO > VCC). ±50 mA Continuous output current, IO (VO 0 to VCC). ±50 mA Continuous current through VCC or GND. ±200 mA Maximum power dissipation = 55°C (in still air) (see Note 2): D package. W N package. W PW package. 0.5 W Storage temperature range, Tstg. to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.
MIN VCC VIH Supply voltage High-level input voltage VCC 3 V VCC 4.5 V VCC 5.5 V VCC 3 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC 3 V VCC 4.5 V VCC 5.5 V VCC 3 V IOL t/v TA Low-level output current Input transition rise or fall rate Operating free-air temperature VCC 4.5 V VCC 0 40 VCC 4.5 V VCC 5.5 V VCC ns/V °C mA NOM 5 MAX 5.5 UNIT V
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