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Details, datasheet, quote on part number:74AC11174N
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| Part: | 74AC11174N |
| Category: | Logic => Flip-Flops => D-Type Flip-Flops |
| Description: | ti 74AC11174, 6-Bit Positive-edge-triggered D-type Flip-flops With Clear |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download 74AC11174N datasheet File size : 88 kB |
| Request For quote: | Find where to buy 74AC11174N
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Datasheet text preview:
74AC11174 HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS146 MARCH 1990 REVISED APRIL 1993
· · · · · ·
Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs
DW OR N PACKAGE (TOP VIEW)
1Q 2Q 3Q GND GND GND GND 4Q 5Q 6Q
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
CLR 1D 2D 3D VCC VCC 4D 5D 6D CLK
description
This device contains six D-type flip-flops and is positive-edge-triggered with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The 74AC11174 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS CLR L H H H CLK X L D X H L X OUTPUT Q L H L QO
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1993, Texas Instruments Incorporated
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74AC11174 HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS146 MARCH 1990 REVISED APRIL 1993
logic symbol
20 CLR CLK 1D 2D 3D 4D 5D 6D 11 19 18 17 14 13 12 R C1 1D 1 2 3 8 9 10 1Q 2Q 3Q 4Q 5Q 6Q
logic diagram (positive logic)
CLR 20
CLK 1D
11 19 1D C1 R 1 1Q
2D
18
1D C1 R 2 2Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 17 3D
1D C1 R 3 3Q
4D
14
1D C1 R 8 4Q
13 5D
1D C1 R
9
5Q
6D
12
1D C1 R 10 6Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±150 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
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74AC11174 HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS146 MARCH 1990 REVISED APRIL 1993
recommended operating conditions
MIN VCC VIH Supply voltage High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V VCC = 4.5 V VCC = 5.5 V VI VO IOH Input voltage Output voltage High-level output current VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V VCC = 4.5 V VCC = 5.5 V 0 40 0 0 3 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC 4 24 24 12 24 24 10 85 ns/ V °C mA mA V V V V NOM 5 MAX 5.5 UNIT V
VIL
Low-level input voltage
IOL t/v TA
Low-level output current Input transition rise or fall rate Operating free-air temperature
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS VCC 3V IOH = 50 µA VOH IOH = 4 mA IOL = 24 mA A IOH = 75 mA IOL = 50 µA VOL IOL = 12 mA IOL = 24 mA 24 mA IOL = 75 mA II ICC VI = VCC or GND VI = VCC or GND, IO = 0 4.5 V 5.5 V 3V 4.5 V 5.5 V 5.5 V 3V 4.5 V 5.5 V 3V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V ± 0.1 8 0.1 0.1 0.1 0.36 0.36 0.36 TA = 25°C MIN 2.9 4.4 5.4 2.58 3.94 4.94 TYP MAX MIN 2.9 4.4 5.4 2.48 3.8 4.8 3.85 0.1 0.1 0.1 0.44 0.44 0.44 1.65 ±1 80 µA µA pF V V MAX UNIT
Ci VI = VCC or GND 5V 4 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
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74AC11174 HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS146 MARCH 1990 REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX fclock tw tsu th Clock frequency Pulse duration duration Setup time before CLK time before CLK Hold time after CLK CLR low CLK high or low Data CLR inactive 0 4.5 6 7 1.5 0 80 MIN 0 4.5 6 7 1.5 0 MAX 80 UNIT MHz ns ns ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX fclock tw tsu th Clock frequency Pulse duration duration Setup time before CLK time before CLK Hold time after CLK CLR low CLK high or low Data CLR inactive 0 4 5 4.5 1.5 0 100 MIN 0 4 5 4.5 1.5 0 MAX 100 UNIT MHz ns ns ns
switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPHL tPLH tPHL CLR CLK Any Q Any Q FROM (INPUT) TO (OUTPUT) MIN 80 3.9 2.4 3.4 TA = 25°C TYP MAX 105 10 7.5 9.6 13.5 9.2 12.7 MIN 80 3.9 2.4 3.4 14.8 10.8 14 MAX UNIT MHz ns ns
switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPHL tPLH tPHL CLR CLK Any Q Any Q FROM (INPUT) TO (OUTPUT) MIN 100 2.9 2.1 2.7 TA = 25°C TYP MAX 125 6.5 4.9 6.2 9.8 6.8 9.2 MIN 100 2.9 2.1 2.7 10.7 7.6 10.1 MAX UNIT MHz ns ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 1 MHz TYP 29 UNIT pF
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74AC11174 HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS146 MARCH 1990 REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
From Output Under Test CL = 50 pF (see Note A) 500 tw VCC Input 50% 50% 0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
Input (see Note B) Timing Input (see Note B) tsu Data Input 50% 50% th VCC 50% 0V Out-of-Phase Output VOLTAGE WAVEFORMS tPHL VCC 0V In-Phase Output tPLH
VCC 50% 50% 0V tPHL 50% VCC VOH 50% VCC VOL tPLH 50% VCC VOH 50% VCC VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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