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Details, datasheet, quote on part number:74AC11191DW
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Datasheet text preview:
74AC11191 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
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Single Down/Up Count Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable with Load Control Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs
DW OR N PACKAGE (TOP VIEW)
t
RCO QA QB GND GND GND GND QC QD MAX/MIN
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
D/U CLK A B VCC VCC C D CTEN LOAD
description
The 74AC11191 is a synchronous, 4-bit binary reversible up/down counter. Synchronous counting operation is provided by clocking all flip-flops simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if the enable input (CTEN) is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down. These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter will be dictated solely by the condition meeting the stable setup and hold times. These counters are fully programmable; that is, the outputs may be preset to any number between 0 and 15 by placing a low on the load input and entering the desired data at the data inputs. The outputs will change to agree with the data inputs independently of the level of the clock input. This feature allows the counter to be used as a modulo-N divider by simply modifying the count length with the preset inputs. Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (15) counting up. The ripple-clock output (RCO) produces a low-level output pulse under those same conditions but only while the clock input is low. The counter can easily be cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation. The 74AC11191 is characterized for operation from 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
74AC11191 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
logic symbol
CTEN D/U CLK 19 12 20 CTRDIV16 G1 M2 [DOWN] 2(CT=0)Z6 M3 [UP] 3(CT=15)Z6 1,2/1,3+ G4 6,1,4 C5 5D [1] [2] [4] [8]
10
MAX/MIN
1
LOAD 11 A B C D 18 17 14 13
RCO
2 3 8 9
QA QB QC QD
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
74AC11191 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
logic diagram (positive logic)
10
MAX/MIN
CTEN
12 1 20 RCO
D/U CLK LOAD A
19 11 18
S C1 1D R
2
QA
B
17
S C1 1D R
3
QB
C
14
S C1 1D R
8
QC
D
13
S C1 1D R
9
QD
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
74AC11191 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
typical load, count, and inhibit sequences
Illustrated below is the following sequence: 1. Load (preset) to binary thirteen 2. Count up to fourteen, fifteen (maximum), zero, one, and two 3. Inhibit 4. Count down to one, zero (minimum), fifteen, fourteen, and thirteen.
LOAD A
B Data Inputs C
D
CLOCK
D/U
CTEN
QA
QB
QC
QD
MAX/MIN
RCO
13
14
15
0
1
2
2 Inhibit
2
1
0
15
14
13
Count Up Load
Count Down
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
74AC11191 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 150 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN VCC VIH Supply voltage High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V IOL Low-level output current Input transition rise or fall rate Operating free-air temperature VCC = 4.5 V VCC = 5.5 V 0 40 VCC = 4.5 V VCC = 5.5V 0 0 3 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC 4 24 24 12 24 24 10 85 ns/V °C mA mA V V V V NOM 5 MAX 5.5 UNIT V
Dt/Dv
TA
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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