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Details, datasheet, quote on part number:74AC11194DW
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Datasheet text preview:
74AC11194 4BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS093 NOVEMBER 1989 REVISED APRIL 1993
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Parallel-to-Serial, Serial-to-Parallel Conversions Left or Right Shifts Parallel Synchronous Loading Direct Overriding Clear Temporary Data Latching Capability Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, and Standard Plastic 300-mil DIPs
DW OR N PACKAGE (TOP VIEW)
t
SR SER QA QB GND GND GND GND QC QD SL SER
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
S0 S1 A B VCC VCC C D CLR CLK
description
This bidirectional shift register features parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation: Parallel (broadside) load Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clocking (do nothing). Synchronous parallel loading is accomplished by applying the 4 bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously, and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode control inputs are low. The 74AC11194 is characterized for operation from 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303 POST OFFICE BOX 1443
· DALLAS, TEXAS 75265 · HOUSTON, TEXAS 772511443
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74AC11194 4BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS093 NOVEMBER 1989 REVISED APRIL 1993
Function Table INPUTS CLEAR L H H H H H H H MODE S1 X X H L L H H L S0 X X H H H L L L CLOCK X L X SERIAL LEFT X X X X X H L X RIGHT X X X H L X X X A X X a X X X X X PARALLEL B X X b X X X X X C X X c X X X X X D X X d X X X X X QA L QA0 a H L QBn QBn QAO OUTPUTS QB L QB0 b QAn QAn Q Cn Q Cn QBO QC L Q C0 c QBn QBn Q Dn Q Dn Q CO QD L Q D0 d Q Cn Q Cn H L Q DO
H = high level (steady state) L = low level (steady state) X = irrelevant (any input, including transitions) = transition from low to high level a,b,c,d = the level of steady-state input at inputs A, B, C, or D, respectively. QAO, QBO, QCO, QDO = the level of QA, QB, QC, or QD, respectively, before the indicated steady-state input conditions were established. QAn, QBn, QCn, QDn = the level of QA, QB, QC, or QD respectively, before the most-recent transition of the clock.
timing clear, load, right-shift, inhibit, and clear sequences
CLK Mode Control Inputs S0 S1 CLR Serial Data Inputs R L A Parallel Data Inputs B C D QA QB Outputs QC QD Shift Right CLR Load Shift Left Inhibit CLR H L H L
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
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74AC11194 4BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS093 NOVEMBER 1989 REVISED APRIL 1993
logic symbol
CLR S0 S1 CLK 12 20 19 11 SRG4 R 0 1 M C4 1 SR SER A B C D SL SER 1 18 17 14 13 10 1, 4D 3, 4D 3, 4D 3, 4D 3, 4D 2, 4D 3 8 9 /2 2 0 3
QA QB QC QD
logic diagram (positive logic)
Parallel Inputs
A Mode Control Inputs S0 S1 19 20 18 B 17 C 14 D 13
SR SER
1
10
SL SER
1S C1 1R R CLK CLR 11 12 2 QA
1S C1 1R R
1S C1 1R R
1S C1 1R R
3 QB QC
8 QD
9
Parallel Outputs
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
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74AC11194 4BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS093 NOVEMBER 1989 REVISED APRIL 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN VCC VIH Supply voltage High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V VIL Low-level input voltage VCC = 4.5 V VCC = 5.5 V VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V IOL VI VO TA Low-level output current Input voltage Output voltage Input transition rise or fall rate Operating free-air temperature VCC = 4.5 V VCC = 5.5 V 0 0 0 40 3 2.1 3.15 3.85 0.9 1.35 1.65 4 24 24 12 24 24 VCC VCC 10 85 V V ns/V °C mA mA V V NOM 5 MAX 5.5 UNIT V
IOH
High-level output current
Dt/Dv
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
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74AC11194 4BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS093 NOVEMBER 1989 REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS VCC 3V IOH = 50 mA VOH IOH = 4 mA IOH = 24 mA mA IOH = 75 mA{ IOL = 50 mA VOL IOL = 12 mA IOL = 24 mA 24 mA IOL = 75 mA{ VI = VCC or GND VI = VCC or GND, VI = VCC or GND IO = 0 4.5 V 5.5 V 3V 4.5 V 5.5 V 5.5 V 3V 4.5 V 5.5 V 3V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 4 ± 0.1 8 0.1 0.1 0.1 0.36 0.36 0.36 MIN 2.9 4.4 5.4 2.58 3.94 4.94 TA = 25°C TYP MAX MIN 2.9 4.4 5.4 2.48 3.8 4.8 3.85 0.1 0.1 0.1 0.44 0.44 0.44 1.65 ±1 80 V V MAX UNIT
II ICC Ci
mA mA
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER fclock tw Clock frequency CLK high Pulse duration CLK low CLR low tsu th t Setup time before CLK time before CLK Hold time after CLK time after CLK Recovery time Select Data Select Data TA = 25°C MIN MAX 0 5.5 5.5 4.5 5 4 1.5 0.5 1 90 MIN 0 5.5 5.5 4.5 5 4 1.5 0.5 1 ns ns ns ns MAX 90 UNIT MHz
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
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