|Category||Semiconductors => Logic => Flip-Flop/Latch/Register => D-Type Latch|
|Part family||74AC16373 16-Bit Transparent D-Type Latches With 3-State Outputs|
|Description||16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85|
|Company||Texas Instruments, Inc.|
|Datasheet||Download 74AC16373 datasheet
|Output Drive (IOL/IOH)(Max)(mA)||24/-24|
|ICC @ Nom Voltage(Max)(mA)||0.08|
|Operating Temperature Range(C)||-40 to 85|
|tpd @ Nom Voltage(Max)(ns)||14.8,10.1|
|Approx. Price (US$)||0.91 | 1ku|
|F @ Nom Voltage(Max)(Mhz)||100|
|Pin nb||Package type||Ind std||JEDEC code||Package qty||Carrier||Device mark||Width (mm)||Length (mm)||Thick (mm)||Pitch (mm)|
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This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding | Doc
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|• Designing With Logic (Rev. C)
Data sheets, which usually give information on device behavior only under recommended operating conditions, may only partially answer engineering questions that arise during the development of systems using logic devices. However, information is frequently | Doc
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Members of the Texas Instruments Widebus TM Family 3-State True Outputs Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacingsdescription
The 'AC16373 are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 74AC16373 is packaged in TI's shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54AC16373 is characterized for operation over the full military temperature range to 125°C. The 74AC16373 is characterized for operation from to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC. 7 V Input voltage range, VI (see Note V to VCC 0.5 V Output voltage range, VO (see Note V to VCC 0.5 V Input clamp current, IIK (VI VI > VCC). ±20 mA Output clamp current, IOK (VO VO > VCC). ±50 mA Continuous output current, IO (VO 0 to VCC). ±50 mA Continuous current through VCC or GND. ±400 mA Maximum power dissipation = 55°C (in still air) (see Note 2): DL package. 1.2 W Storage temperature range, Tstg. to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
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