Members of the Texas Instruments Widebus TM Family 3-State True Outputs Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Pin Spacings
description
The 'AC16543 are 16-bit registered transceivers that contain two sets of D-type latches for temporary storage of data flowing in either direction. They can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low 28 29 enter data from or to output data to B. Having CEAB low and LEAB low makes the A-to-B latches transparent; a subsequent low-to-high transition at LEAB puts the A latches in the storage mode. Data flow from A is similar, but requires using the CEBA, LEBA, and OEBA inputs. The 74AC16543 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54AC16543 is characterized for operation over the full military temperature range to 125°C. The 74AC16543 is characterized for operation from to 85°C.
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UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
FUNCTION TABLE (each 8-bit section) INPUTS CEAB LEAB OEAB OUTPUT L H
A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. Output level before the indicated steady-state input conditions were established
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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