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Details, datasheet, quote on part number: 74AC16646DLR
CategorySemiconductors => Logic => Buffer/Driver/Transceiver => Registered Transceiver
Part family74AC16646 16-Bit Bus Transceivers And Registers With 3-State Outputs
TitleRegistered Transceivers
Description16-Bit Bus Transceivers And Registers With 3-State Outputs 56-SSOP -40 to 85
CompanyTexas Instruments, Inc.
ROHSNot Compliant
DatasheetDownload 74AC16646DLR datasheet
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
56DLSSOPR-PDSO-G 7.4918.412.59.635
Application notes
• Input and Output Characteristics of Digital Integrated Circuits
This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given i | Doc
• TI IBIS File Creation, Validation, and Distribution Processes
The Input/Output Buffer Information Specification (IBIS), also known as ANSI/EIA-656, has become widely accepted among electronic design automation (EDA) vendors, semiconductor vendors, and system des | Doc
• Live Insertion
Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must | Doc
• Implications of Slow or Floating CMOS Inputs (Rev. C)
When using CMOS and BiCMOS devices, a designer must understand the characteristics of these families and the way inputs and outputs behave in systems. It is very important for the designer to follow a | Doc
• Shelf-Life Evaluation of Lead-Free Component Finishes
The integrated circuit (IC) industry is converting to lead (Pb)-free termination finishes for leadframe-based packages. IC component users need to know the maximum length of time that components can b | Doc
• Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | Doc
• Designing With Logic (Rev. C)
Data sheets, which usually give information on device behavior only under recommended operating conditions, may only partially answer engineering questions that arise during the development of systems | Doc
• CMOS Power Consumption and CPD Calculation (Rev. B)
Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a res | Doc
• Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
Though low power consumption is a feature of CMOS devices, sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supp | Doc


Features, Applications

Members of the Texas Instruments Widebust Family Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings


The 'AC16646 are 16-bit bus transceivers that consist of D-type flip-flops and control circuitry, with 3-state outputs arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the bus transceivers and registers.

Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select controls (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, or B, may be driven at a time. The 74AC16646 is packaged in the TI shrink small-outline package, which provides twice the functionality of standard small-outline packages in the same printed-circuit-board area. The 54AC16646 is characterized for operation over the full military temperature range to 125C. The 74AC16646 is characterized for operation from to 85C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303


FUNCTION TABLE INPUTS OE DIR CLKAB or L CLKBA L X SAB SBA A1A8 Input Unspecified Input Output Input DATA I/O B1B8 Unspecified Input Output OPERATION OR FUNCTION Store A, B unspecified{ Store B, A unspecified{ Store A and B data Isolation, hold storage Real-time B data to A bus Stored B data to A bus Real-time A data to B Bus

Stored A data to bus The data-output functions may be enabled or disabled by various signals OE or DIR. Data-input functions are always enabled, i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.


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0-C     D-L     M-R     S-Z