|Category||Logic => Bus Interface => CMOS/BiCMOS->AC/ACT Family|
|Description||18-bit Bus Interface Flip-flops With 3-state Outputs|
|Company||Texas Instruments, Inc.|
|Datasheet||Download 74AC16823 datasheet
Members of the Texas Instruments Widebus TM Family Provides Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Pin Spacingsdescription
These 18-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, parity bus interfacing, and working registers. The 'AC16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock.
The output enable (OE) input can be used to place the outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 74AC16823 is packaged in TI's shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54AC16374 is characterized for operation over the full military temperature range to 125°C. The 74AC16823 is characterized for operation from to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303FUNCTION TABLE (each 9-bit stage) INPUTS OE CLR CLKEN CLK OUTPUT Q0 Z
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC. 7 V Input voltage range, VI (see Note V to VCC 0.5 V Output voltage range, VO (see Note V to VCC 0.5 V Input clamp current, IIK (VI VI > VCC). ±20 mA Output clamp current, IOK (VO VO > VCC). ±50 mA Continuous output current, IO (VO 0 to VCC). ±50 mA Continuous current through VCC or GND. ±450 mA Maximum power package dissipation = 55°C (in still air)(see Note 2): DL package. 1.4 W Storage temperature range, Tstg. to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
54AC16823 MIN VCC VIH Supply voltage High-level input voltage VCC 3 V VCC 4.5 V VCC 5.5 V VCC 3 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC 3 V VCC 4.5 V VCC 5.5 V VCC 3 V IOL t/v Low-level output current Input transition rise or fall rate VCC 4.5 V VCC 0 55 VCC 4.5 V VCC 5.5 V VCC NOM 5 MAX 5.5 74AC16823 MIN VCC ns/V °C mA NOM 5 MAX 5.5 UNIT V
TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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