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Part: 74ACT11020

Category:
 Logic
   -> Gates
             -> CMOS/BiCMOS->AC/ACT Family

Description: Dual 4-input Positive-nand Gates

Company: Texas Instruments, Inc.

Datasheet: Download 74ACT11020 datasheet     File size : 275 kB

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Datasheet text preview:
54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES
SCAS016A ­ D2957, JUNE 1987 ­ REVISED APRIL 1993

· · · · · ·

Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

54ACT11020 . . . J PACKAGE 74ACT11020 . . . D OR N PACKAGE (TOP VIEW)

1B 1A 1Y GND 2Y 2D 2C

1 2 3 4 5 6 7

14 13 12 11 10 9 8

NC 1C 1D VCC 2A 2B NC

54ACT11020 . . . FK PACKAGE (TOP VIEW)

These devices contain two independent 4-input NAND gates. They perform the Boolean functions Y = ASBSCSD or Y = A + B + C + D in positive logic. The 54ACT11020 is characterized for operation over the full military temperature range of ­ 55°C to 125°C. The 74ACT11020 is characterized for operation from ­ 40°C to 85°C.
FUNCTION TABLE (each gate) INPUTS A H L X X X B H X L X X C H X X L X D H X X X L OUTPUT Y L H H H H

NC NC 1B NC 1A

4 5 6 7 8

3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

1C 1D NC VCC 2A 2B NC NC NC 2C
NC ­ No internal connection

description

logic diagram (positive logic)
1A 1B 1C 1D 2A 2B 2C 2D 1Y

1Y GND NC 2Y 2D
1Y 2Y 3 5 2Y
Copyright © 1993, Texas Instruments Incorporated

logic symbol
1A 1B 1C 1D 2A 2B 2C 2D 2 1 13 12 10 9 7 6 &

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.

EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303

· DALLAS, TEXAS 75265

2­1

54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES
SCAS016A ­ D2957, JUNE 1987 ­ REVISED APRIL 1993

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 0.5 V to 6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

recommended operating conditions
54ACT11020 MIN VCC VIH VIL VI VO IOH IOL Dt /Dv TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature 0 ­ 55 0 0 4.5 2 0.8 VCC VCC ­ 24 24 10 125 0 ­ 40 0 0 MAX 5.5 74ACT11020 MIN 4.5 2 0.8 VCC VCC ­ 24 24 10 85 MAX 5.5 UNIT V V V V V mA mA ns/ V °C

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS IOH = ­ 50 mA mA VOH IOH = ­ 24 mA mA IOH = ­ 50 mA IOH = ­ 75 mA IOL = 50 mA 50 mA VOL IOL = 24 mA 24 mA IOL = 50 mA IOL = 75 mA II ICC VI = VCC or GND VI = VCC or GND, IO = 0 VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V ± 0.1 4 0.9 ±1 80 1 0.1 0.1 0.36 0.36 0.1 0.1 0.5 0.5 1.65 1.65 ±1 40 1 MIN 4.4 5.4 3.94 4.94 TA = 25°C TYP MAX 54ACT11020 MIN 4.4 5.4 3.7 4.7 3.85 3.85 0.1 0.1 0.44 0.44 V MAX 74ACT11020 MIN 4.4 5.4 3.8 4.8 V MAX UNIT

mA mA
mA pF

DICC§

One input at 3.4 V, Other inputs at GND or VCC

Ci VI = VCC or GND 5V 3.5 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

2­2

POST OFFICE BOX 655303

· DALLAS, TEXAS 75265

54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES
SCAS016A ­ D2957, JUNE 1987 ­ REVISED APRIL 1993

switching characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL FROM (INPUT) Any TO (OUTPUT) Y MIN 1.5 1.5 TA = 25°C TYP MAX 5.6 6.1 8.5 8.4 54ACT11020 MIN 1.5 1.5 MAX 9.5 9.8 74ACT11020 MIN 1.5 1.5 MAX 9.1 9.2 UNIT ns

operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per gate TEST CONDITIONS CL = 50 pF, f = 1 MHz TYP 27 UNIT pF

PARAMETER MEASUREMENT INFORMATION
From Output Under Test CL = 50 pF (see Note A) 500 Output Input (see Note B) tPHL 3V 1.5 V 1.5 V 0V tPLH VOH 50% VCC VOL LOAD CIRCUIT VOLTAGE WAVEFORMS

50% VCC

NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303

· DALLAS, TEXAS 75265

2­3

54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES
SCAS016A ­ D2957, JUNE 1987 ­ REVISED APRIL 1993

2­4

POST OFFICE BOX 655303

· DALLAS, TEXAS 75265

IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.

Copyright © 1998, Texas Instruments Incorporated




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