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Part: 74ACT11074D
Category:
Logic
-> Flip-Flops
-> D-Type Flip-Flops
Description: ti 74ACT11074, Dual Positive-edge-triggered D-type Flip-flops With Clear And Preset
Company: Texas Instruments, Inc.
Datasheet: Download 74ACT11074D datasheet File size : 275 kB
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74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCAS498A DECEMBER 1986 REVISED APRIL 1996
D D D D D
Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N)
D, DB, OR N PACKAGE (TOP VIEW)
1PRE 1Q 1Q GND 2Q 2Q 2PRE
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1CLK 1D 1CLR VCC 2CLR 2D 2CLK
description
This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs. The 74ACT11074 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS PRE L H L H H H CLR H L L H H H CLK X X X L D X X X H L X OUTPUTS Q H L H{ H L Q0 Q L H H{ L H Q0
This configuration is unstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
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1
74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCAS498A DECEMBER 1986 REVISED APRIL 1996
logic symbol
1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 1 14 13 12 7 8 9 10 6 2Q S C1 1D R 3 1Q 2 1Q
5
2Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . 1.25 W DB package . . . . . . . . . . . . . . . . . . . 0.5 W N package . . . . . . . . . . . . . . . . . . . . 1.1 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.
recommended operating conditions
MIN VCC VIH VIL VI VO IOH IOL Dt/Dv TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature 0 40 0 0 4.5 2 0.8 VCC VCC 24 24 10 85 MAX 5.5 UNIT V V V V V mA mA ns/V °C
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCAS498A DECEMBER 1986 REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = 50 mA 50 mA VOH IOH = 24 mA 24 mA IOH = 75 mA IOL = 50 mA 50 mA VOL IOL = 24 mA 24 mA IOL = 75 mA VI = VCC or GND VI = VCC or GND, One input at 3.4 V, IO = 0 Other inputs at GND or VCC TEST CONDITIONS CONDITIONS VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V ±0.1 4 0.9 0.1 0.1 0.36 0.36 MIN 4.4 5.4 3.94 4.94 TA = 25°C TYP MAX MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 ±1 40 1 V V MAX UNIT
II ICC
mA mA
mA pF
DICC
Ci VI = VCC or GND 5V 3.5 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX fclock tw tsu th Clock frequency Pulse duration duration Setup time before CLK time before CLK Hold time after CLK PRE or CLR low CLK low or high Data high or low PRE or CLR inactive 0 5 5 4.5 2 0 100 MIN 0 5 5 4.5 2 0 MAX 100 UNIT MHz ns ns ns
switching characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) MIN 100 1.5 PRE or CLR or CLR CLK Q or Q or Q or Q or 1.5 1.5 1.5 TA = 25°C TYP MAX 125 5.7 6.6 6 5.7 8.9 11.3 8.5 8 MIN 100 1.5 1.5 1.5 1.5 9.6 12.5 9.4 8.8 MAX UNIT MHz ns ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per flip-flop TEST CONDITIONS CL = 50 pF, f = 1 MHz TYP 30 UNIT pF
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3
74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCAS498A DECEMBER 1986 REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
From Output Under Test CL = 50 pF (see Note A) 500 tw 3V Input 1.5 V 1.5 V 0V LOAD CIRCUIT VOLTAGE WAVEFORMS 3V 1.5 V tPLH Timing Input (see Note B) tsu Data Input 1.5 V 3V 1.5 V 0V th 3V 1.5 V 0V VOLTAGE WAVEFORMS Out-of-Phase Output 50% VCC tPHL In-Phase Output 50% VCC 1.5 V 0V tPHL VOH 50% VCC VOL tPLH VOH 50% VCC VOL
Input (see Note B)
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright © 1998, Texas Instruments Incorporated
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