|
Details, datasheet, quote on part number:74ACT11378
| |
Datasheet text preview:
74ACT11378 HEX DTYPE FLIPFLOP WITH CLOCK ENABLE
SCAS185A AUGUST 1990 REVISED APRIL 1993
· · · · · · · · ·
Inputs Are TTL-Voltage Compatible Contains Six D-Type Flip-Flops Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, and Standard Plastic 300-mil DIPs
DW OR N PACKAGE (TOP VIEW)
1Q 2Q 3Q GND GND GND GND 4Q 5Q 6Q
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
CLKEN 1D 2D 3D VCC VCC 4D 5D 6D CLK
description
These circuits are positive-edge-triggered D-type flip-flops with a clock-enable input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the clock-enable input (CLKEN) is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock inputs are at either the high or low level, the data (D) input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the clock-enable (CLKEN) input. The 74ACT11378 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each flip-flop) INPUTS CLKEN H L L X CLK X L D X H L X OUTPUT Q QO H L QO
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
74ACT11378 HEX DTYPE FLIPFLOP WITH CLOCK ENABLE
SCAS185A AUGUST 1990 REVISED APRIL 1993
logic symbol
CLKEN CLK 1D 2D 3D 4D 5D 6D 20 11 19 18 17 14 13 12 G1 1C2 2D 1 2 3 8 9 10 1Q 2Q 3Q 4Q 5Q 6Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
CLKEN 20
CLK
11
C1 1D 19 1D C1 2D 18 1D C1 3D 17 1D C1 4D 14 1D C1 1D C1 6D 12 1D
1
1Q
2
2Q
3
3Q
8
4Q
5D
13
9
5Q
10
6Q
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
74ACT11378 HEX DTYPE FLIPFLOP WITH CLOCK ENABLE
SCAS185A AUGUST 1990 REVISED APRIL 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±150 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 40 0 0 4.5 2 0.8 VCC VCC 24 24 10 85 NOM 5 MAX 5.5 UNIT V V V V V mA mA ns/V °C
TA Operating free-air temperature NOTE 2: Unused or floating inputs must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = 50 µA µA VOH IOH = 24 mA mA IOH = 75 mA IOL = 50 µA 50 µA VOL IOL = 24 mA 24 mA IOL = 75 mA VI = VCC or GND VI = VCC or GND, One input at 3.4 V, Other inputs at VCC or GND IO = 0 TEST CONDITIONS CONDITIONS VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V ± 0.1 8 0.9 0.1 0.1 0.36 0.36 MIN 4.4 5.4 3.94 4.94 TA = 25°C TYP MAX MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 ±1 80 1 µA µA mA pF V V MAX UNIT
II ICC ICC§
Ci VI = VCC or GND 5V 4.5 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
74ACT11378 HEX DTYPE FLIPFLOP WITH CLOCK ENABLE
SCAS185A AUGUST 1990 REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX fclock tw tsu th Clock frequency Pulse duration Setup time before CLK time, before CLK Hold time after CLK time, after CLK CLK high or low Data CLKEN high or low Data CLKEN high or low 0 5 5 4.5 0.5 1 100 MIN 0 5 5 4.5 0.5 1 MAX 100 UNIT MHz ns ns ns
switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL FROM (INPUT) TO (OUTPUT) TA = 25°C MIN TYP MAX 100 CLK Any Q 2.8 3.7 130 5.9 7.3 6.8 9.2 MIN 100 2.8 3.7 9 10.7 MAX UNIT MHz ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 1 MHz TYP 31 UNIT pF
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
74ACT11378 HEX DTYPE FLIPFLOP WITH CLOCK ENABLE
SCAS185A AUGUST 1990 REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
Timing Input (see Note B) 3V 1.5 V 0 tsu 500 Data Input 1.5 V th 3V 1.5 V 0 SETUP AND HOLD TIMES LOAD CIRCUIT 3V 1.5 V tPLH 0 tw Low-Level Input 3V 1.5 V 1.5 V 0 Out-of-Phase Output PULSE DURATION 50% VCC tPHL In-Phase Output 50% VCC 1.5 V 0 tPHL VOH 50% VCC VOL tPLH VOH 50% VCC VOL
From Output Under Test CL = 50 pF (see Note A)
Input (see Note B) 3V High-Level Input 1.5 V 1.5 V
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. For testing fmax and pulse duration: tr = 1 to 3 ns, tf = 1 to 3 ns. C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
|
|
