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Details, datasheet, quote on part number:74ACT11379
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Datasheet text preview:
74ACT11379 QUAD D-TYPE FLIP-FLOP WITH CLOCK ENABLE
SCAS103 JANUARY 1990 REVISED APRIL 1993
· · · · · · · · ·
Inputs Are TTL-Voltage Compatible Contains Four Flip-Flops with Double-Rail Outputs Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small Outline Packages, and Standard Plastic 300-mil DIPs
DW OR N PACKAGE (TOP VIEW)
t
1Q 2Q 2Q GND GND GND GND 3Q 3Q 4Q
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
1Q CLKEN 1D 2D VCC VCC 3D 4D CLK 4Q
description
These circuits are positive-edge-triggered D-type flip-flops with a clock-enable input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if CLKEN is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the CLKEN input. The 74ACT11379 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each flip-flop) INPUTS CLKEN H L L X CLK X L D X H L X OUTPUTS Q Q0 H L Q0 Q Q0 L H Q0
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1993, Texas Instruments Incorporated
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74ACT11379 QUAD D-TYPE FLIP-FLOP WITH CLOCK ENABLE
SCAS103 JANUARY 1990 REVISED APRIL 1993
logic symbol
CLKEN CLK 19 12 G1 IC2 20 2D 1 2 3 8 9 10 11 1Q 1Q 2Q 2Q 3Q 3Q 4Q 4Q
logic diagram (positive logic)
CLKN 19
1D
18
2D
17
CLK
12
3D
14
1D
18
C1 1D C1 1D C1 1D
20 1 2 3 8 9 10 11
1Q 1Q 2Q 2Q 3Q 3Q 4Q 4Q
4D
13
2D
17
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3D
14
4D
13
C1 1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
} Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN VCC VIH VIL VI VO IOH IOL Dt/Dv TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature 0 40 0 0 4.5 2 0.8 VCC VCC 24 24 10 85 MAX 5.5 UNIT V V V V V mA mA ns/V °C
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74ACT11379 QUAD D-TYPE FLIP-FLOP WITH CLOCK ENABLE
SCAS103 JANUARY 1990 REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = 50 mA mA VOH IOH = 24 mA mA IOH = 75 mA{ IOL = 50 mA 50 mA VOL IOL = 24 mA 24 mA IOL = 75 mA{ VI = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, , Other inputs at GND or VCC TEST CONDITIONS CONDITIONS VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V ± 0.1 8 0.9 0.1 0.1 0.36 0.36 MIN 4.4 5.4 3.94 4.94 TA = 25°C TYP MAX MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 ±1 80 1 V V MAX UNIT
II ICC
mA mA
mA pF
DICC
Ci VI = VCC or GND 5V 4 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX fclock tw Clock frequency Pulse duration duration CLK high CLK low Data tsu th Setup time, before CLK Hold time, after CLK CLKEN high CLKEN low CLKEN inactive or active, data 0 5 5 5 3.5 3.5 0 100 MIN 0 5 5 5 3.5 3.5 0 ns ns MAX 100 UNIT MHz ns
switching characteristics over recommended ranges of supply voltage and operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL FROM (INPUT) TO (OUTPUT) MIN 100 CLK 2.2 Any Q or Q or 3.1 TA = 25°C TYP MAX 125 5 7.2 6.6 9.8 MIN 100 2.2 3.1 7.4 11.2 MAX UNIT MHz ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 1 MHz TYP 38 UNIT pF
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74ACT11379 QUAD D-TYPE FLIP-FLOP WITH CLOCK ENABLE
SCAS103 JANUARY 1990 REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
From Output Under Test C L = 50 pF (see Note A) 500 Low-Level Input 1.5 V 1.5 V 0 VOLTAGE WAVEFORMS PULSE DURATIONS 3V Input Timing Input (see Note B) tsu Data Input 3V 1.5 V 0 th 3V 1.5 V 1.5 V 0 SETUP AND HOLD TIMES tPHL Out-of-Phase Output (see Note C) 50% tPLH In-Phase Output 50% tPHL VOH 50% VOL tPLH VOH 50% VOL 1.5 V 1.5 V 0 High-Level Input 3V 1.5 V tw 3V 1.5 V 0
LOAD CIRCUIT
PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Zo = 50 , tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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