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Details, datasheet, quote on part number:74ACT11534NT
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Datasheet text preview:
54ACT11534, 74ACT11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS038A D2957, JULY 1987 REVISED APRIL 1993
· · · · · · · · ·
Eight D-Type Flip-Flops in a Single Package 3-State Bus Driving Inverting Outputs Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic SmallOutline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
54ACT11534 . . . JT PACKAGE 74ACT11534 . . . DW OR NT PACKAGE (TOP VIEW)
t
1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
OC 1D 2D 3D 4D VCC VCC 5D 6D 7D 8D CLK
54ACT11534 . . . FK PACKAGE (TOP VIEW)
description
These eight flip-flops feature 3-state outputs designed for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the ACT11534 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the complement of the logic levels at the D inputs. The ACT11534 is functionally equivalent to the ACT11373 except for having inverted outputs. An output-control input (OC) is used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up components. The output control (OC) does not affect the internal operations of the flip-flops. Old data can be retained, or new data can be entered while the outputs are in the high-impedance state. The 54ACT11534 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74ACT11534 is characterized for operation from 40°C to 85°C.
3D 4D VCC NC VCC 5D 6D 2D 1D OC NC 1Q 2Q 3Q
5 6 7 8 9 10 4 3 2 1 28 27 26 25 24 23 22 21 20 11 19 12 13 14 15 16 17 18
7D 8D CLK NC 8Q 7Q 6Q
NC No internal connection
OC L L L H
4Q GND GND NC GND GND 5Q
FUNCTION TABLE (each flip-flop) INPUTS CLK L X D H L X X OUTPUT Q L H Q0 Z
Copyright © 1993, Texas Instruments Incorporated
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
21
54ACT11534, 74ACT11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS038A D2957, JULY 1987 REVISED APRIL 1993
logic symbol
OC CLK 1D 2D 3D 4D 5D 6D 7D 8D 24 13 23 22 21 20 17 16 15 14 EN C1 1D 1 2 3 4 9 10 11 12 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
logic diagram (positive logic)
OC CLK 24 13 C1 1D C1 1D C1 1D C1 1D C1 1D C1 1D C1 1D C1 1D 12 11 10 9 4 3 2 1
1D
23
1Q
2D
22
2Q
3D
21
3Q
4D This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 5D
20
4Q
17
5Q
6D
16
6Q
7D
15
7Q
8D Pin numbers shown are for the DW, JT, and NT packages.
14
8Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
54ACT11534, 74ACT11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS038A D2957, JULY 1987 REVISED APRIL 1993
recommended operating conditions
54ACT11534 MIN VCC VIH VIL VI VO IOH IOL Dt /Dv TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature 0 55 0 0 4.5 2 0.8 VCC VCC 24 24 10 125 0 40 0 0 MAX 5.5 74ACT11534 MIN 4.5 2 0.8 VCC VCC 24 24 10 85 MAX 5.5 UNIT V V V V V mA mA ns/ V °C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS IOH = 50 mA mA VOH IOH = 24 mA mA IOH = 50 mA{ IOH = 75 mA{ IOL = 50 mA 50 mA VOL IOL = 24 mA 24 mA IOL = 50 mA{ IOL = 75 mA{ IOZ II ICC VO = VCC or GND VI = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at GND or VCC VI = VCC or GND VO = VCC or GND VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 4 ± 0.5 ± 0.1 8 0.9 ± 10 ±1 160 1 0.1 0.1 0.36 0.36 0.1 0.1 0.5 0.5 1.65 1.65 ±5 ±1 80 1 MIN 4.4 5.4 3.94 4.94 TA = 25°C TYP MAX 54ACT11534 MIN 4.4 5.4 3.7 4.7 3.85 3.85 0.1 0.1 0.44 0.44 V MAX 74ACT11534 MIN 4.4 5.4 3.8 4.8 V MAX UNIT
mA mA mA
mA pF pF
DICC}
Ci
Co 5V 10 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
23
54ACT11534, 74ACT11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS038A D2957, JULY 1987 REVISED APRIL 1993
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX fclock tw tsu th Clock frequency Pulse duration, CLK low or CLK high Setup time, data before CLK Hold time, data after CLK 0 9 3 5.5 55 54ACT11534 MIN 0 9 3 5.5 MAX 55 74ACT11534 MIN 0 9 3 5.5 MAX 55 UNIT MHz ns ns ns
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN 55 CLK 1.5 Any Q Any Q Any Q 1.5 1.5 OC OC 1.5 1.5 1.5 TA = 25°C TYP MAX 70 8.5 8.5 7.5 7.5 11 8 12.7 13.3 12 12.2 12.9 11.2 54ACT11534 MIN 55 1.5 1.5 1.5 1.5 1.5 1.5 15.7 16.3 14.2 14.5 13.9 12.5 MAX 74ACT11534 MIN 55 1.5 1.5 1.5 1.5 1.5 1.5 14.5 15 13.3 13.5 13.5 12 MAX UNIT MHz ns ns ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per flip flop Power dissipation capacitance per flip-flop Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF 50 pF, f = 1 MHz MHz TYP 92 82 UNIT pF
24
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
54ACT11534, 74ACT11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SCAS038A D2957, JULY 1987 REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VCC GND
LOAD CIRCUIT Timing Input (see Note B) tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Data Input tsu 1.5 V 3V 1.5 V 0V th 3V 1.5 V 0V
Input (see Note B) tPLH In-Phase Output tPHL Out-of-Phase Output
3V 1.5 V 1.5 V 0V tPHL 50% VCC VOH 50% VCC VOL tPLH 50% VCC VOH 50% VCC VOL
Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note C) Output Waveform 2 S1 at GND (see Note C)
3V 1.5 V tPZL tPLZ 50% VCC tPHZ 80% VCC VOH 20% VCC 1.5 V 0V
[ VC C
VOL
tPZH
50% VCC
[0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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