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Part: 74ACT16240DL
Category:
Logic
-> Buffers/Drivers
-> Inverting Buffers and Drivers
Description: ti 74ACT16240, 16-Bit Buffers/drivers With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 74ACT16240DL datasheet File size : 232 kB
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Datasheet text preview:
SN54ACT16240, 74ACT16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS137C JULY 1989 REVISED NOVEMBER 1996
D D D D D D D D
Members of the Texas Instruments Widebus TM Family Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Spacings
SN54ACT16240 . . . WD PACKAGE 74ACT16240 . . . DL PACKAGE (TOP VIEW)
description
The SN54ACT16240 and 74ACT16240 are 16-bit buffers or line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide inverting outputs and symmetrical active-low output-enable (OE) inputs.
1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE
The 74ACT16240 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ACT16240 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74ACT16240 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each section) INPUTS OE L L H A H L X OUTPUT Y L H Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1996, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
1
SN54ACT16240, 74ACT16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS137C JULY 1989 REVISED NOVEMBER 1996
logic symbol
1OE 2OE 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1 48 25 24 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 4 1 3 1 2 EN1 EN2 EN3 EN4 1 1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ACT16240, 74ACT16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS137C JULY 1989 REVISED NOVEMBER 1996
logic diagram (positive logic)
1OE 1 3OE 2 25
1A1
47
1Y1
3A1
36
13 3Y1 14
1A2
46
3
1Y2
3A2
35
3Y2
1A3
44
5
1Y3
3A3
33
16
3Y3
1A4
43
6 1Y4 3A4
32
17
3Y4
2OE
48
4OE 8
24
2A1
41
2Y1
4A1
30
19
4Y1
2A2
40
9
2Y2
4A2
29
20
4Y2
2A3
38
11 2Y3
27 4A3 26
22
4Y3
2A4
37
12
2Y4
23
4A4
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.2 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN54ACT16240, 74ACT16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS137C JULY 1989 REVISED NOVEMBER 1996
recommended operating conditions (see Note 3)
SN54ACT16240 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 55 0 0 4.5 2 0.8 VCC VCC 24 24 10 125 0 40 0 0 NOM 5 MAX 5.5 74ACT16240 MIN 4.5 2 0.8 VCC VCC 24 24 10 85 NOM 5 MAX 5.5 UNIT V V V V V mA mA ns/V °C
TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS IOH = 50 µA 50 µA VOH IOH = 24 mA 24 mA IOH = 50 mA IOH = 75 mA IOL = 50 µA 50 µA VOL IOL = 24 mA 24 mA IOL = 50 mA IOL = 75 mA II IOZ ICC ICC Ci Co VI = VCC or GND VO = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 4.5 12 ±0.1 ±0.5 8 0.9 ±1 ±10 160 1 0.1 0.1 0.36 0.36 0.1 0.1 0.5 0.5 1.65 1.65 ±1 ±5 80 1 µA µA µA mA pF pF TA = 25°C MIN TYP MAX 4.4 5.4 3.94 4.94 SN54ACT16240 MIN 4.4 5.4 3.7 4.7 3.85 3.85 0.1 0.1 0.44 0.44 V MAX 74ACT16240 MIN 4.4 5.4 3.8 4.8 V MAX UNIT
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ACT16240, 74ACT16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS137C JULY 1989 REVISED NOVEMBER 1996
switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) A TO (OUTPUT) Y Y Y MIN 2.3 4.1 2.6 3.3 5.9 5.1 TA = 25°C TYP MAX 5 6.7 5.6 6.7 8.3 7.4 7.7 9.2 8.5 10.2 11 9.9 SN54ACT16240 MIN 2 3 2 2.5 4.5 4 MAX 9.5 11.5 10.1 12.2 12.7 12 74ACT16240 MIN 2.3 4.1 2.6 3.3 5.9 5.1 MAX 8.5 10.2 9.4 11.4 12 10.7 UNIT ns ns ns
OE OE
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per driver dissipation capacitance per driver Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF 50 pF, f = 1 MHz MHz TYP 38 9 UNIT pF
PARAMETER MEASUREMENT INFORMATION
2 × VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VC C GND
LOAD CIRCUIT
Output Control (low-level enabling) 3V Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B)
3V 1.5 V tPZL tPLZ 50% VCC tPHZ 80% VCC VOH 20% VCC 1.5 V 0V
Input tPHL
1.5 V
1.5 V 0V tPLH VOH 50% VCC 50% VCC VOL
[ VC C
VOL
tPZH
Output
50% VCC
[0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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