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Details, datasheet, quote on part number:74ACT16864DL
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Datasheet text preview:
54ACT16864, 74ACT16864 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS244A JUNE 1992 REVISED APRIL 1996
D D D D D D D D
Members of the Texas Instruments Widebus TM Family Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Spacings
54ACT16864 . . . DW PACKAGE 74ACT16864 . . . DL PACKAGE (TOP VIEW)
description
The 'ACT16864 are 18-bit inverting transceivers designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. The 'ACT16864 can be used as two 9-bit transceivers or one 18-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the output-enable (OEAB or OEBA) inputs.
1OEAB 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 1B7 GND 1B8 1B9 GND GND 2B1 2B2 GND 2B3 2B4 2B5 VCC 2B6 2B7 GND 2B8 2B9 2OEAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEBA 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 1A7 GND 1A8 1A9 GND GND 2A1 2A2 GND 2A3 2A4 2A5 VCC 2A6 2A7 GND 2A8 2A9 2OEBA
The 74ACT16864 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16864 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74ACT16864 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE (each 9-bit section) INPUTS OEAB H L H OEBA L H H OPERATION B data to A bus A data to B bus Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and WIdebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1996, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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54ACT16864, 74ACT16864 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS244A JUNE 1992 REVISED APRIL 1996
logic symbol
56 1OEBA 1OEAB 2OEBA 2OEAB 1A1 28 55 1 29 EN1 EN2 EN3 EN4 1 1 1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 2A1 54 52 51 49 48 47 45 44 41 3 1 1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 40 38 37 36 34 33 31 30 4 17 19 20 21 23 24 26 27 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2 3 5 6 8 9 10 12 13 16 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 2B1 2 1B1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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54ACT16864, 74ACT16864 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS244A JUNE 1992 REVISED APRIL 1996
logic diagram
1OEBA 56 2OEBA 29
1OEAB
1
2OEAB
28
1A1
55
2
1B1
2A1
41
16
2B1
To Eight Other Channels
To Eight Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±450 mA Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16864 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 0 4.5 2 0.8 VCC VCC 24 24 10 125 0 40 0 0 NOM 5 MAX 5.5 74ACT16864 MIN 4.5 2 0.8 VCC VCC 24 24 10 85 NOM 5 MAX 5.5 UNIT V V V V V mA mA ns/V °C
TA Operating free-air temperature 55 NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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54ACT16864, 74ACT16864 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS244A JUNE 1992 REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS IOH = 50 µA 50 µA VOH IOH = 24 mA 24 mA IOH = 75 mA IOL = 50 µA 50 µA VOL IOL = 24 mA 24 mA IOL = 75 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND Control inputs A or B ports VI = VCC or GND VO = VCC or GND VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 5V 4.5 17 ±0.1 ±0.5 8 0.9 0.1 0.1 0.36 0.36 MIN 4.4 5.4 3.94 4.94 TA = 25°C TYP MAX 54ACT16864 MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 ±1 ±5 80 1 MAX 74ACT16864 MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 ±1 ±5 80 1 µA µA µA mA pF pF V V MAX UNIT
II IOZ ICC ICC§ Ci Cio
Control inputs A or B ports
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) A or B or TO (OUTPUT) B or A or B or A or B or A or TA = 25°C MIN TYP MAX 1.6 3.7 2.2 3.1 5.1 5 7 8.1 8.2 10.2 8.6 8.3 8.9 10 10.1 12.4 10.1 9.7 54ACT16864 MIN 1.6 3.7 2.2 3.1 5.1 5 MAX 10.2 11.3 11.1 13.8 10.8 10.3 74ACT16864 MIN 1.6 3.7 2.2 3.1 5.1 5 MAX 10.2 11.3 11.1 13.8 10.8 10.3 UNIT ns ns ns
OEAB or OEBA or OEBA OEAB or OEBA or OEBA
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per transceiver dissipation capacitance per transceiver Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF 50 pF, f = 1 MHz MHz TYP 56 9 UNIT pF
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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POST OFFICE BOX 655303
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54ACT16864, 74ACT16864 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS244A JUNE 1992 REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VCC GND
LOAD CIRCUIT 3V Timing Input tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH VOLTAGE WAVEFORMS Data Input tsu 1.5 V 1.5 V 0V th 3V 1.5 V 0V
3V Input 1.5 V tPLH In-Phase Output tPHL Out-of-Phase Output 50% VCC 50% VCC 1.5 V 0V tPHL VOH 50% VCC VOL tPLH VOH 50% VCC VOL
3V 1.5 V tPZL tPLZ 50% VCC tPHZ 80% VCC VOH 20% VCC 1.5 V 0V
[ VC C
VOL
50% VCC
[0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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