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Details, datasheet, quote on part number:74ACT16952DLR
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Datasheet text preview:
54ACT16952, 74ACT16952 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS159C JANUARY 1991 REVISED APRIL 1996
D D D D D D D D D
Members of the Texas Instruments Widebus TM Family Inputs Are TTL-Voltage Compatible Noninverting Outputs Two 16-Bit, Back-to-Back Registers Store Data Flowing in Both Directions Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings
54ACT16952 . . . WD PACKAGE 74ACT16952 . . . DL PACKAGE (TOP VIEW)
description
The 'ACT16952 are 16-bit registered transceivers 21 36 that contain two sets of D-type flip-flops for 22 35 temporary storage of data flowing in either 23 34 direction. They can be used as two 8-bit 24 33 transceivers or one 16-bit transceiver. Data on the 25 32 A or B bus is stored in registers on the low-to-high 26 31 transition of the clock (CLKAB or CLKBA) input, 27 30 provided that the clock-enable (CEAB or CEBA) 28 29 input is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port. To avoid false clocking of the flip-flops, CEAB (or CEBA) should not be switched from low to high while CLKAB (or CLKBA) is low. The 74ACT16952 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16952 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74ACT16952 is characterized for operation from 40°C to 85°C.
1OEAB 1CLKAB 1CEAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2CEAB 2CLKAB 2OEAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
1OEBA 1CLKBA 1CEBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2CEBA 2CLKBA 2OEBA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright © 1996, Texas Instruments Incorporated
· DALLAS, TEXAS 75265
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54ACT16952, 74ACT16952 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS159C JANUARY 1991 REVISED APRIL 1996
FUNCTION TABLE INPUTS CEAB H X L L CLKAB X H OEAB L L L L A X X L H OUTPUT B B0 B0 L H
X X H X Z A-to-B data flow is shown; B-to-A data flow is similar but uses CEBA, CLKBA, and OEBA. Level of B before the indicated steady-state input conditions were established
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POST OFFICE BOX 655303
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54ACT16952, 74ACT16952 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS159C JANUARY 1991 REVISED APRIL 1996
logic symbol
1OEBA 1CEBA 1CLKBA 1OEAB 3 1CEAB 1CLKAB 2OEBA 31 2CEBA 2CLKBA 2OEAB 2CEAB 2CLKAB 1A1 30 28 26 27 5 2 29 56 54 55 1 EN3 G1 1C5 EN4 G2 2C6 EN9 G7 7C11 EN10 G8 8C12 3 6D 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 6 8 9 10 12 13 14 15 9 12D 2A2 2A3 2A4 2A5 2A6 2A7 2A8 16 17 19 20 21 23 24 11D 10 41 40 38 37 36 34 33 2B2 2B3 2B4 2B5 2B6 2B7 2B8 5D 4 51 49 48 47 45 44 43 42 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 52 1B1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
54ACT16952, 74ACT16952 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS159C JANUARY 1991 REVISED APRIL 1996
logic diagram (positive logic)
1OEBA 1CEBA 1CLKBA 56
54 55 1 3 2
1OEAB 1CEAB 1CLKAB
1A1
5
C1 1D 52 1B1
C1 1D
To Seven Other Channels 2OEBA 2CEBA 2CLKBA 29
31 30 28 26 27
2OEAB 2CEAB 2CLKAB
2A1
15
C1 1D 42 2B1
C1 1D
To Seven Other Channels
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
54ACT16952, 74ACT16952 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS159C JANUARY 1991 REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16952 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 0 4.5 2 0.8 VCC VCC 24 24 10 125 0 40 0 0 NOM 5 MAX 5.5 74ACT16952 MIN 4.5 2 0.8 VCC VCC 24 24 10 85 NOM 5 MAX 5.5 UNIT V V V V V mA mA ns/V °C
TA Operating free-air temperature 55 NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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