|
|
Part: 74ALVCH162268ZQLR
Category:
Logic
-> Bus Exchangers
-> Universal Bus Exchangers (UBEs)
Description: ti SN74ALVCH162268, 12-Bit to 24-Bit Registered Bus Exchanger With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 74ALVCH162268ZQLR datasheet File size : 67 kB
Request For quote: Find where to buy 74ALVCH162268ZQLR
Datasheet text preview:
SN74ALVCH162268 12 BIT TO 24 BIT REGISTERED BUS EXCHANGER WITH 3 STATE OUTPUTS
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
D Member of the Texas Instruments D D D D D D D
Widebus Family Operates From 1.65 V to 3.6 V Max tpd of 4.8 ns at 3.3 V ±24 mA Output Drive at 3.3 V B-Port Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A)
DGG OR DL PACKAGE (TOP VIEW)
description/ordering information
This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH162268 is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower-frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The select (SEL) line is synchronous with CLK and selects 1B or 2B input data for the A outputs.
OEA CLKEN1B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 CLKEN2B SEL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
OEB CLKENA2 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 CLKENA1 CLK
For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). These control terminals are registered, so bus direction changes are synchronous with CLK. ORDERING INFORMATION
TA SSOP - DL -40°C to 85 C 85°C TSSOP - DGG VFGBA - GQL VFGBA - ZQL (Pb-free) Tape and reel PACKAGE Tube Tape and reel Tape and reel ORDERABLE PART NUMBER SN74ALVCH162268DL SN74ALVCH162268DLR SN74ALVCH162268GR SN74ALVCH162268KR 74ALVCH162268ZQLR VH2268 ALVCH162268 ALVCH162268 TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
SN74ALVCH162268 12 BIT TO 24 BIT REGISTERED BUS EXCHANGER WITH 3 STATE OUTPUTS
description/ordering information (continued)
The B outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
GQL OR ZQL PACKAGE (TOP VIEW) 1 A B C D E F G H J K 2 3 4 5 6
terminal assignments
1 A B C D E F G H J K 2B3 2B1 A2 A4 A6 A7 A9 A11 1B1 1B3 2 CLKEN1B 2B2 A1 A3 A5 A8 A10 A12 1B2 CLKEN2B GND VCC GND SEL GND VCC GND CLK 3 OEA GND VCC GND 4 OEB GND VCC GND 5 CLKENA2 2B5 2B7 2B9 2B11 1B11 1B9 1B7 1B5 CLKENA1 6 2B4 2B6 2B8 2B10 2B12 1B12 1B10 1B8 1B6 1B4
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74ALVCH162268 12 BIT TO 24 BIT REGISTERED BUS EXCHANGER WITH 3 STATE OUTPUTS
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
Function Tables
OUTPUT ENABLE INPUTS CLK OEA H H L L OEB H L H L OUTPUTS A Z Z Active Active 1B, 2B Z Active Z Active
A-TO-B STORAGE (OEB = L) INPUTS CLKENA1 H L L X X CLKENA2 H L L L L CLK X A X L H L H OUTPUTS 1B 1B0 L H X X 2B 2B0 X X L H
Output level before the indicated steady-state input conditions were established Two CLK edges are needed to propagate data B-TO-A STORAGE (OEA = L) INPUTS CLKEN1B H X L L X X CLKEN2B X H L L L L CLK X X SEL H L H H L L 1B X X L H X X 2B X X X X L H OUTPUT A A0 A0 L H L H
Output level before the indicated steady-state input conditions were established
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
SN74ALVCH162268 12 BIT TO 24 BIT REGISTERED BUS EXCHANGER WITH 3 STATE OUTPUTS
logic diagram (positive logic)
29 CLK 2 CLKEN1B 27 CLKEN2B CLKENA1 30 55 CLKENA2 56 OEB C1
C1
1D
SEL OEA
28 1D 1 CE 1D C1 C1 1D 23 1B1
G1 1 1
CE C1 1D 1D 6 2B1
8 A1
CE C1 1D
CE C1 1D
CE C1 1D 1 of 12 Channels
Pin numbers shown are for the DGG and DL packages.
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74ALVCH162268 12 BIT TO 24 BIT REGISTERED BUS EXCHANGER WITH 3 STATE OUTPUTS
SCES018J - AUGUST 1995 - REVISED AUGUST 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
Others parts begin by 74
74-1 74-2 74-3 74-4 74-5 74-6 74-7 74-8 74-9 74-10 74-11 74-12 74-13 74-14 74-15 74-16 74-17 74-18 74-19 74-20 74-21 74-22 74-23 74-24 74-25 74-26 74-27 74-28 74-29 74-30 74-31 74-32 74-33 74-34 74-35 74-36 74-37 74-38 74-39 74-40 74-41 74-42 74-43 74-44 74-45 74-46 74-47 74-48 74-49 74-50 74-51 74-52 74-53 74-54 74-55 74-56 74-57 74-58 74-59 74-60 74-61 74-62
|
|
|
