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Part: 74ALVCH32244ZKER
Category:
Logic
-> Buffers/Drivers
-> Non-Inverting Buffers and Drivers
Description: ti SN74ALVCH32244, 32-Bit Buffer/driver With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 74ALVCH32244ZKER datasheet File size : 67 kB
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Datasheet text preview:
SCES281C - OCTOBER 1999 - REVISED AUGUST 2003
SN74ALVCH32244 32 BIT BUFFER/DRIVER WITH 3 STATE OUTPUTS
D Member of the Texas Instruments D D D D
Widebus+ Family Operates From 1.65 V to 3.6 V Max tpd of 3 ns at 3.3 V ±24-mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
D Latch-Up Performance Exceeds 100 mA Per D
JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101)
description/ordering information
This 32-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH32244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. ORDERING INFORMATION
TA -40°C to 85°C PACKAGE LFBGA - GKE LFBGA - ZKE (Pb-free) Tape and reel ORDERABLE PART NUMBER SN74ALVCH32244KR 74ALVCH32244ZKER ACH244 TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each 4-bit buffer) INPUTS OE L L H A H L X OUTPUT Y H L Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SCES281C - OCTOBER 1999 - REVISED AUGUST 2003
SN74ALVCH32244 32 BIT BUFFER/DRIVER WITH 3 STATE OUTPUTS
GKE OR ZKE PACKAGE (TOP VIEW) 1 A B C D E F G H J K L M N P R T 2 3 4 5 6
terminal assignments
1 A B C D E F G H J K L M N P R T 1Y2 1Y4 2Y2 2Y4 3Y2 3Y4 4Y2 4Y3 5Y2 5Y4 6Y2 6Y4 7Y2 7Y4 8Y2 8Y3 2 1Y1 1Y3 2Y1 2Y3 3Y1 3Y3 4Y1 4Y4 5Y1 5Y3 6Y1 6Y3 7Y1 7Y3 8Y1 8Y4 3 1OE GND VCC GND GND VCC GND 4OE 5OE GND VCC GND GND VCC GND 8OE 4 2OE GND VCC GND GND VCC GND 3OE 6OE GND VCC GND GND VCC GND 7OE 5 1A1 1A3 2A1 2A3 3A1 3A3 4A1 4A4 5A1 5A3 6A1 6A3 7A1 7A3 8A1 8A4 6 1A2 1A4 2A2 2A4 3A2 3A4 4A2 4A3 5A2 5A4 6A2 6A4 7A2 7A4 8A2 8A3
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SCES281C - OCTOBER 1999 - REVISED AUGUST 2003
SN74ALVCH32244 32 BIT BUFFER/DRIVER WITH 3 STATE OUTPUTS
logic diagram (positive logic)
1OE A3 3OE A2 H4
1A1
A5
1Y1
3A1
E5
E2
3Y1
1A2
A6
A1
1Y2
3A2
E6
E1
3Y2
1A3
B5
B2
1Y3
3A3
F5
F2
3Y3
1A4
B6
B1
1Y4
3A4
F6
F1
3Y4
2OE
A4
4OE C2
H3
2A1
C5
2Y1
4A1
G5
G2
4Y1
2A2
C6
C1
2Y2
4A2
G6
G1
4Y2
2A3
D5
D2
2Y3
4A3
H6
H1
4Y3
2A4
D6
D1
2Y4
4A4
H5
H2
4Y4
5OE
J3
7OE J2
T4
5A1
J5
5Y1
7A1
N5
N2
7Y1
5A2
J6
J1
5Y2
7A2
N6
N1
7Y2
5A3
K5
K2
5Y3
7A3
P5
P2
7Y3
5A4
K6
K1
5Y4
7A4
P6
P1
7Y4
6OE
J4
8OE L2
T3
6A1
L5
6Y1
8A1
R5
R2
8Y1
6A2
L6
L1
6Y2
8A2
R6
R1
8Y2
6A3
M5
M2
6Y3
8A3
T6
T1
8Y3
6A4
M6
M1
6Y4
8A4
T5
T2
8Y4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SCES281C - OCTOBER 1999 - REVISED AUGUST 2003
SN74ALVCH32244 32 BIT BUFFER/DRIVER WITH 3 STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3): GKE/ZKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN Operating VCC Supply voltage Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI VO Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 0 0 1.65 1.5 0.65 × VCC 1.7 2 0.35 × VCC 0.7 0.8 VCC VCC -4 -8 -12 -24 4 8 12 24 10 ns/V mA mA V V V V MAX 3.6 V UNIT
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SCES281C - OCTOBER 1999 - REVISED AUGUST 2003
SN74ALVCH32244 32 BIT BUFFER/DRIVER WITH 3 STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 µA IOH = -4 mA VOH IOH = -8 mA IOH = -12 mA IOH = -24 mA IOL = 100 µA VOL IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA II VI = VCC or GND VI = 0.58 V VI = 1.07 V VI = 0.7 V II(hold) VI = 1.7 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V IOZ ICC ICC Control inputs Ci Data inputs VI = VCC or GND 3.3 V VO = VCC or GND VI = VCC or GND, One input at VCC - 0.6 V, IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3.6 V 1.65 V 1.65 V 2.3 V 2.3 V 3V 3V 3.6 V 3.6 V 3.6 V 3 V to 3.6 V 3 6 pF 25 -25 45 -45 75 -75 ±500 ±10 80 750 µA µA µA µA MIN TYP MAX UNIT VCC-0.2 1.2 1.7 2.2 2.4 2.2 0.2 0.45 0.7 0.4 0.55 ±5 µA V V
Co Outputs VO = VCC or GND 3.3 V 7 pF All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten FROM (INPUT) A OE TO (OUTPUT) Y Y VCC = 1.8 V ± 0.15 V MIN § § § MAX § § § VCC = 2.5 V ± 0.2 V MIN 1 1 1 MAX 3.7 5.7 5.2 VCC = 2.7 V MIN MAX 3.6 5.4 4.6 VCC = 3.3 V ± 0.3 V MIN 1 1 1 MAX 3 4.4 4.1 ns ns ns UNIT
tdis Y OE § This information was not available at the time of publication.
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 0, f = 10 MHz VCC = 1.8 V TYP § § VCC = 2.5 V TYP 16 4 VCC = 3.3 V TYP 19 5 UNIT pF
§ This information was not available at the time of publication.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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