|
Details, datasheet, quote on part number:74ALVCH32374ZKER
| |
Datasheet text preview:
SN74ALVCH32374 32 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS
SCES283C - OCTOBER 1999 - REVISED AUGUST 2003
D Member of the Texas Instruments D D D D
Widebus+ Family Operates From 1.65 V to 3.6 V Max tpd of 4.2 ns at 3.3 V ±24 mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
D Latch-Up Performance Exceeds 100 mA Per D
JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101)
description/ordering information
This 32-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH32374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. The output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. ORDERING INFORMATION
TA -40°C to 85°C PACKAGE LFBGA - GKE LFBGA - ZKE (Pb-free) Tape and reel ORDERABLE PART NUMBER SN74ALVCH32374KR 74ALVCH32374ZKER ACH374 TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each flip-flop) INPUTS OE L L L H CLK H or L X D H L X X OUTPUT Q H L Q0 Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SCES283C - OCTOBER 1999 - REVISED AUGUST 2003
SN74ALVCH32374 32 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS
GKE OR ZKE PACKAGE (TOP VIEW) 1 A B C D E F G H J K L M N P R T 2 3 4 5 6 A B C D E F G H J K L M N P R T
terminal assignments
1 1Q2 1Q4 1Q6 1Q8 2Q2 2Q4 2Q6 2Q7 3Q2 3Q4 3Q6 3Q8 4Q2 4Q4 4Q6 4Q7 2 1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q8 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q8 3 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 4 1CLK GND VCC GND GND VCC GND 2CLK 3CLK GND VCC GND GND VCC GND 4CLK 5 1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D8 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D8 6 1D2 1D4 1D6 1D8 2D2 2D4 2D6 2D7 3D2 3D4 3D6 3D8 4D2 4D4 4D6 4D7
logic diagram (positive logic)
A3 1OE A4 1CLK A5 1D1 C1 1D A2 1Q1 2CLK C1 2D1 E5 1D E2 2Q1 2OE H4 H3
To Seven Other Channels J3 3OE J4 3CLK J5 3D1 C1 1D J2 3Q1 4CLK N5 4D1 4OE T4 T3
To Seven Other Channels
C1 1D
N2
4Q1
To Seven Other Channels
To Seven Other Channels
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74ALVCH32374 32 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS
SCES283C - OCTOBER 1999 - REVISED AUGUST 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3): GKE/ZKE package . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN Operating VCC Supply voltage Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI VO Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 0 0 1.65 1.5 0.65 × VCC 1.7 2 0.35 × VCC 0.7 0.8 VCC VCC -4 -8 -12 -24 4 8 12 24 10 ns/V mA mA V V V V MAX 3.6 V UNIT
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SCES283C - OCTOBER 1999 - REVISED AUGUST 2003
SN74ALVCH32374 32 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 µA IOH = -4 mA VOH IOH = -8 mA IOH = -12 mA IOH = -24 mA IOL = 100 µA VOL IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA II VI = VCC or GND VI = 0.58 V VI = 1.07 V VI = 0.7 V II(hold) VI = 1.7 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V IOZ ICC ICC Control inputs Ci Data inputs VI = VCC or GND 3.3 V VO = VCC or GND VI = VCC or GND, One input at VCC - 0.6 V, IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3.6 V 1.65 V 1.65 V 2.3 V 2.3 V 3V 3V 3.6 V 3.6 V 3.6 V 3 V to 3.6 V 3 6 pF 25 -25 45 -45 75 -75 ±500 ±10 80 750 µA µA µA µA MIN TYP MAX UNIT VCC-0.2 1.2 1.7 2.2 2.4 2.2 0.2 0.45 0.7 0.4 0.55 ±5 µA V V
Co Outputs VO = VCC or GND 3.3 V 7 pF All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V ± 0.15 V MIN fclock tw tsu th Clock frequency Pulse duration, CLK high or low Setup time, data before CLK Hold time, data after CLK § § § MAX § VCC = 2.5 V ± 0.2 V MIN 3.3 2.1 0.6 MAX 150 3.3 2.2 0.5 VCC = 2.7 V MIN MAX 150 3.3 1.9 0.5 VCC = 3.3 V ± 0.3 V MIN MAX 150 MHz ns ns ns UNIT
§ This information was not available at the time of publication.
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74ALVCH32374 32 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS
SCES283C - OCTOBER 1999 - REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER fmax tpd ten FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN MAX VCC = 2.5 V ± 0.2 V MIN 150 1 1 1 5.3 6.2 5.3 MAX VCC = 2.7 V MIN 150 4.9 5.9 4.7 MAX VCC = 3.3 V ± 0.3 V MIN 150 1 1 1.2 4.2 4.8 4.3 MAX MHz ns ns ns UNIT
CLK OE
Q Q
tdis Q OE This information was not available at the time of publication.
operating characteristics, TA = 25°C
PARAMETER Power dissipation capacitance Outputs enabled Outputs disabled CL = 50 pF, f = 10 MHz TEST CONDITIONS VCC = 1.8 V TYP VCC = 2.5 V TYP 31 16 VCC = 3.3 V TYP 30 18 pF UNIT
Cpd
This information was not available at the time of publication.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
|
|
