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Part: 74ALVCH32973ZKER
Category:
Logic
-> Transceivers
-> Standard Transceivers
Description: ti SN74ALVCH32973, 16-Bit Bus Transceiver And Transparent D-type Latch With 8 Independent Buffers
Company: Texas Instruments, Inc.
Datasheet: Download 74ALVCH32973ZKER datasheet File size : 67 kB
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Datasheet text preview:
SN74ALVCH32973 16 BIT BUS TRANSCEIVER AND TRANSPARENT D TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS
SCES436A - APRIL 2003 - REVISED AUGUST 2003
D Member of the Texas Instruments D
Widebus+ Family Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
D Latch-Up Performance Exceeds 250 mA Per D
JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101)
description/ordering information
This device contains eight independent noninverting buffers and a 16-bit noninverting bus transceiver and D-type latch designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH32973 is particularly suitable for demultiplexing an address/data bus into a dedicated address bus and dedicated data bus. The device is used where there is asynchronous bidirectional communication between the A and B data bus, and the address signals are latched and buffered on the Q bus. The control-function implementation minimizes external timing requirements. This device can be used as one 8-bit buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one 16-bit transceiver, and one 16-bit latch. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The transceiver output-enable (TOE) input can be used to disable the transceivers so that the A and B buses effectively are isolated. When the latch-enable (LE) input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE) input can be used to place the nine Q outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, LOE and TOE should be tied to VCC through pullup resistors; the minimum values of the resistors are determined by the current-sinking capability of the drivers. The eight independent noninverting buffers perform the Boolean function Y = D and are independent of the state of DIR, TOE, LE, and LOE. The A and B I/Os and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA -40°C to 85°C PACKAGE LFBGA - GKE LFBGA - ZKE (Pb-free) Tape and reel ORDERABLE PART NUMBER SN74ALVCH32973KR 74ALVCH32973ZKER ACH973 TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SCES436A - APRIL 2003 - REVISED AUGUST 2003
SN74ALVCH32973 16 BIT BUS TRANSCEIVER AND TRANSPARENT D TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS
GKE OR ZKE PACKAGE (TOP VIEW) 1 A B C D E F G H J K L M N P R T 2 3 4 5 6
terminal assignments
1 A B C D E F G H J K L M N P R T 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2 D1 Y1 D2 Y2 D3 Y3 D4 Y4 D5 Y5 D6 Y6 D7 Y7 D8 Y8 3 1TOE GND VCC GND GND VCC GND 1LE 2TOE GND VCC GND GND VCC GND 2LE 4 1DIR GND VCC GND GND VCC GND 1LOE 2DIR GND VCC GND GND VCC GND 2LOE 5 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 6 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8
NC - No internal connection
Function Tables
INPUTS TOE L L H DIR L H X OPERATION B data to A bus A data to B bus A bus and B bus Isolation
INPUTS LOE L L L H LE H H L X A H L X X
OUTPUT Q H L Qo Z
INPUT D L H
OUTPUT Y L H
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74ALVCH32973 16 BIT BUS TRANSCEIVER AND TRANSPARENT D TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS
SCES436A - APRIL 2003 - REVISED AUGUST 2003
logic diagram (positive logic)
1DIR A4
A3 1LOE H4
1TOE
1LE
H3
One of Eight Channels C1 A6 1D 1A1 A1 1Q1
A5
1B1
To Seven Other Channels
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SCES436A - APRIL 2003 - REVISED AUGUST 2003
SN74ALVCH32973 16 BIT BUS TRANSCEIVER AND TRANSPARENT D TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS
logic diagram (positive logic) (continued)
2DIR J4
J3 2LOE T4
2TOE
2LE
T3
One of Eight Channels C1 J6 1D 2A1 J1 2Q1
J5
2B1
To Seven Other Channels
One of Eight Channels D1 A2 B2 Y1
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74ALVCH32973 16 BIT BUS TRANSCEIVER AND TRANSPARENT D TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS
SCES436A - APRIL 2003 - REVISED AUGUST 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI: Except I/O and D input ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V I/O and D input ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output-voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3): GKE/ZKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 0 VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 1.65 0.65 × VCC 1.7 2 0.35 × VCC 0.7 0.8 VCC VCC -4 -12 -12 -24 4 12 12 24 10 ns/V mA mA V V V V MAX 3.6 UNIT V
High-level input voltage
VIL VI VO
Low-level input voltage Input voltage Output voltage
IOH
High-level output current
IOL
Low-level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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