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Part: 74FCT163H374CPVCT
Category:
Logic
-> Flip-Flops
-> D-Type (3-State) Flip-Flops
Description: ti CY74FCT163H374, 16-Bit Edge-triggered D-type Flip-flops With Bus-hold And 3-State Output
Company: Texas Instruments, Inc.
Datasheet: Download 74FCT163H374CPVCT datasheet File size : 180 kB
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Datasheet text preview:
Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered.
CY74FCT163374 CY74FCT163H374
SCCS050 - March 1997 - Revised March 2000
16-Bit Registers
Functional Description
These devices are 16-bit D-type registers designed for use as buffered registers in high-speed, low power bus applications. These devices can be used as two independent 8-bit registers or as a single 16-bit register by connecting the output Enable (OE) and Clock (CLK) inputs. The outputs are 24-mA balanced output drivers with current limiting resistors to reduce the need for external terminating resistors, and provide for minimal undershoot and reduced ground bounce. Flow-through pinout and small shrink packaging aid in simplifying board layout. The CY74FCT163H374 has "bus hold" on the data inputs, which retains the input's last state whenever the source driving the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs. The CY74FCT163374 is designed with inputs and outputs capable of being driven by 5.0V buses, allowing its use in mixed voltage systems as a translator. The outputs are also designed with a power off disable feature enabling its use in applications requiring live insertion.
Features
· Low power, pin-compatible replacement for LCX and LPT families · 5V tolerant inputs and outputs · 24 mA balanced drive outputs · Power-off disable outputs permits live insertion · Edge-rate control circuitry for reduced noise · FCT-C speed at 5.2 ns · Latch-up performance exceeds JEDEC standard no. 17 · Typical output skew 2000V CY74FCT163H374 · Bus hold on data inputs · Eliminates the need for external pull-up or pull-down resistors · Devices with bus hold are not recommended for translating rail-to-rail CMOS signals to 3.3V logic levels
Logic Block Diagrams CY74FCT163374, CY74FCT163H374
Pin Configuration
SSOP/TSSOP Top View
1OE 1O1 1O2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1CLK 1 D1 1 D2
1OE
2OE
GND 1O3
1O4
GND 1 D3
1 D4
1CLK 1D1
2CLK
D
1O1
2 D1
D
2O1
VCC 1O5
1O6
VCC 1 D5
1 D6
C
C
GND
1O7 1O8 2O1
GND
1 D7 1 D8 2 D1 2 D2
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
2O2
GND 2O3
2O4
GND 2 D3
2 D4
VCC 2O5
2O6
VCC 2 D5
2 D6
GND 2O7
2O8 2OE
GND 2 D7
2 D8 2CLK
Lite Drive is a trademark of Cypress Semiconductor Corporation.
Copyright
© 2000, Texas Instruments Incorporated
CY74FCT163374 CY74FCT163H374
Function Table[1]
Inputs D X X L H L H CLK L H OE H H L L H H Outputs O Z Z L H Z Z Load Register Function High-Z
Maximum Ratings[3, 4]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .... -55°C to +125°C Ambient Temperature with Power Applied ........ -55°C to +125°C Supply Voltage Range .... 0.5V to +4.6V DC Input Voltage ....... -0.5V to +7.0V DC Output Voltage .... -0.5V to +7.0V DC Output Current (Maximum Sink Current/Pin) ... -60 to +120 mA Power Dissipation .......... 1.0W Description
Pin Description
Name D CLK OE O Data Inputs
[2]
Operating Range
Range Industrial Ambient Temperature -40°C to +85°C VCC 2.7V to 3.6V
Clock Inputs Three-State Output Enable Inputs (Active LOW) Three-State Outputs
Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter VIH VIL VH VIK IIH IIL IOZH IOZL IOS IOFF ICC ICC Description Input HIGH Voltage Input LOW Voltage Input Hysteresis
[6]
Test Conditions All Inputs
Min. 2.0
Typ.[5]
Max. 5.5 0.8
Unit V V mV V µA µA µA µA mA µA µA µA
100 VCC=Min., IIN=18 mA VCC=Max., VI=5.5 VCC=Max., VI=GND VCC=Max., VOUT=5.5V VCC=Max., VOUT=GND VCC=Max., VOUT=GND VCC=0V, VOUT4.5V VIN0.2V, VIN>VCC0.2V VIN=VCC0.6V[8] VCC=Max. VCC=Max. 0.1 2.0 60 135 0.7 1.2 ±1 ±1 ±1 ±1 240 ±100 10 30
Input Clamp Diode Voltage Input HIGH Current Input LOW Current High Impedance Output Current (Three-State Output pins) High Impedance Output Current (Three-State Output pins) Shor t Circuit Current[7] Power-Off Disable Quiescent Power Supply Current Quiescent Power Supply Current (TTL inputs HIGH)
Notes: 1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don't Care. Z = HIGH Impedance. = LOW-to-HIGH Transition. 2. On the CY74FCT163H374, these pins have "bus hold." 3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. 4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground 5. Typical values are at VCC=3.3V, TA = +25°C ambient. 6. This parameter is specified but not tested. 7. Not more than one output should be shor ted at a time. Duration of shor t should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shor ting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 8. Per TTL driven input; all other inputs at VCC or GND.
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CY74FCT163374 CY74FCT163H374
Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter VIH VIL VH VIK IIH IIL IBBH IBBL IBHHO IBHLO IOZH IOZL IOS IOFF ICC ICC Description Input HIGH Voltage Input LOW Voltage Input Hysteresis
[6]
Test Conditions All Inputs
Min. 2.0
Typ.[5]
Max. VCC 0.8
Unit V V mV V µA µA µA µA
100 VCC=Min., IIN=18 mA VCC=Max., VI=VCC
[9]
Input Clamp Diode Voltage Input HIGH Current Input LOW Current Bus Hold Sustain Current on Bus Hold Input
0.7
1.2 ±100 ±100
VCC=Min.
VI=2.0V VI=0.8V
50 +50 ±500 ±1 ±1 60 135 240 ±100 +40 +350
Bus Hold Overdrive Current on Bus Hold Input[9] High Impedance Output Current (Three-State Output pins) High Impedance Output Current (Three-State Output pins) Shor t Circuit Current[7] Power-Off Disable Quiescent Power Supply Current Quiescent Power supply Current (TTL inputs HIGH)
VCC=Max., VI=1.5V VCC=Max., VOUT=VCC VCC=Max., VOUT=GND VCC=Max., VOUT=GND VCC=0V, VOUT4.5V VIN<0.2V VIN=VCC 0.6V[8] VCC=Max. VCC=Max.
µA µA µA mA µA µA µA
Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter IODL IODH VOH Description Output LOW Dynamic Current[7] Test Conditions VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V VCC=Min., IOH= 0.1 mA VCC=Min., IOH= 8 mA VCC=3.0V, IOH= 24 mA VOL Output LOW Voltage VCC=Min., IOL= 0.1mA VCC=Min., IOL= 24 mA
Notes: 9. Pins with bus hold are described in Pin Description. 10. VOH=VCC0.6V at rated current.
Min. 45 45 VCC0.2 2.4
[10]
Typ.[5]
Max. 110 110
Unit mA mA V
Output HIGH Dynamic Current[7] Output HIGH Voltage
3.0 3.0 0.2 0.3 0.55
V V V
2.0
Capacitance[6](TA = +25°C, f = 1.0 MHz)
Parameter CIN COUT Description Input Capacitance Output Capacitance VIN = 0V VOUT = 0V Test Conditions Typ.[5] 4.5 5.5 Max. 6.0 8.0 Unit pF pF
3
CY74FCT163374 CY74FCT163H374
Power Supply Characteristics
Parameter ICCD Description Dynamic Power Supply Current[11] Total Power Supply Current[12] Test Conditions VCC=Max., One Input Toggling, VIN=VCC or 50% Duty Cycle, VIN=GND Outputs Open, OE=GND VCC=Max., f1=10 MHz, 50% VIN=VCC or Duty Cycle, Outputs Open, One VIN=GND Bit Toggling, OE=GND VIN=VCC0.6V or VIN=GND VCC=Max., f1=2.5 MHz, 50% VIN=VCC or Duty Cycle, Outputs Open, Six- VIN=GND teen Bits Toggling, OE=GND VIN=VCC0.6V or VIN=GND Typ.[5] 50 Max. 75 Unit µA/MHz
IC
0.5 0.5 2.0 2.0
0.8 0.8 3.0[13] 3.3[13]
mA mA mA mA
Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[14,15]
CY74FCT163374A CY74FCT163H374A Parameter tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSK(O) Description Propagation Delay Clock to Output Output Enable Time Output Disable Time Input Setup time Input Hold time Output Skew[17] Min. 1.5 1.5 1.5 2.0 1.5 0.5 Max. 6.5 6.5 5.5 CY74FCT163374C CY74FCT163H374C Min. 1.5 1.5 1.5 2.0 1.5 0.5 Max. 5.2 5.5 5.0 Unit ns ns ns ns ns ns Fig. No.[16] 1, 3 1, 7, 8 1, 7, 8 1, 4 1. 4 --
Notes: 11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 12. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC+ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 14. Minimum limits are specified but not tested on Propagation Delays. 15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%. 16. See "Parameter Measurement Information" in the General Information section. 17. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
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CY74FCT163374 CY74FCT163H374
Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[14,15]
CY74FCT163LD374[18] CY74FCT163LDH374 Parameter tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSK(O) Description Propagation Delay Clock to Q Output Output Enable Time Output Disable Time Input Setup time Input Hold time Output Skew
[17]
CY74FCT163LD374A[18] CY74FCT163LDH374A Min. 1.5 1.5 1.5 2.0 1.5 Max. 6.5 6.5 5.5 Unit ns ns ns ns ns 0.5 ns Fig. No.[16] 1, 3 1, 7, 8 1, 7, 8 1, 4 1, 4 --
Min. 1.5 1.5 1.5 2.0 1.5
Max. 10 12.5 8.0
0.5
Note: 18. For Lite Drive devices the load capacitance is 30 pF. For all others it is 50 pF.
Ordering Information CY74FCT163374
Speed (ns) 5.2 6.5 Ordering Code CY74FCT163374CPACT CY74FCT163374CPVC/PVCT CY74FCT163374APACT Package Name Z48 O48 Z48 Package Type 48-Lead (240-Mil) TSSOP 48-Lead (300-Mil) SSOP 48-Lead (240-Mil) TSSOP Industrial Operating Range Industrial
Ordering Information CY74FCT163H374
Speed (ns) 5.2 Ordering Code 74FCT163H374CPACT CY74FCT163H374CPVC 74FCT163H374CPVCT Package Name Z48 O48 O48 Package Type 48-Lead (240-Mil) TSSOP 48-Lead (300-Mil) SSOP 48-Lead (300-Mil) SSOP Operating Range Industrial
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