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Details, datasheet, quote on part number:74FCT163H501CPACT
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Datasheet text preview:
Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered.
CY74FCT163501 CY74FCT163H501
SCCS047 - January 1998 - Revised March 2000
18-Bit Registered Transceivers
· Eliminates the need for external pull-up or pull-down resistors
Features
· Low power, pin-compatible replacement for LCX and LPT families · 5V tolerant inputs and outputs · 24 mA balanced drive outputs · Power-off disable outputs permits live insertion · Edge-rate control circuitry for reduced noise · FCT-C speed at 4.6 ns · Latch-up performance exceeds JEDEC standard no. 17 · ESD > 2000V per MIL-STD-883D, Method 3015 · Typical output skew < 250ps · Industrial temperature range of 40°C to +85°C · TSSOP (19.6-mil pitch) or SSOP (25-mil pitch) · Typical Volp (ground bounce) performance exceeds Mil Std 883D · VCC = 2.7V to 3.6V
Functional Description
These 18-bit universal bus transceivers can be operated in transparent, latched or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. OEAB performs the output enable function on the B por t. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA, LEBA, and CLKBA. The output buffers are designed with a power-off disable feature to allow live insertion of boards. THE CY74FCT163501 has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors, as well as provides for minimal undershoot and reduced ground bounce. The CY74FCT163501 is ideal for driving transmission lines. The CY74FCT163H501 is a 24-mA balanced output par t, that has "bus hold" on the data inputs. The device retains the input's last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.
CY74FCT163501 Features: · Balanced output drivers: 24 mA · Reduced system switching noise · Typical VOLP (ground bounce) <0.6V at VCC = 3.3V, TA= 25°C CY74FCT163H501 Features: · Bus hold retains the last active state · Devices with bus hold are not recommended for translating rail-to-rail CMOS signals to 3.3V logic levels
Functional Block Diagram; CY74FCT163501, CY74FCT163H501
Pin Configuration
SSOP/TSSOP Top View
OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A 10 A 11 A 12 GND A 13 A 14 A 15 VCC A 16 A 17 GND A 18 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND FCT163501-2
OEAB CLKBA LEBA OEBA CLKAB LEAB
C C D
A1
D
B1
C D
C D
TO 17 OTHER CHANNELS
FCT163501-1
Copyright
© 2000, Texas Instruments Incorporated
CY74FCT163501 CY74FCT163H501
Pin Description
Name OEAB OEBA LEAB LEBA CLKAB CLKBA A B Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A Three-State Outputs[1] B-to-A Data Inputs or A-to-B Three-State Outputs[1]
Maximum Ratings[6, 7]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .... -55°C to +125°C Ambient Temperature with Power Applied ........ -55°C to +125°C DC Input Voltage ....... -0.5V to +7.0V DC Output Voltage .... -0.5V to +7.0V DC Output Current (Maximum Sink Current/Pin) ... -60 to +120 mA Power Dissipation .......... 1.0W Static Discharge Voltage...........>2001V (per MIL-STD-883, Method 3015)
Operating Range Function Table[2, 3]
Inputs OEAB L H H H H H H
1. 2. 3.
Outputs A X L H L H L H X X B Z L H L H B[4] B[5]
Range Industrial
Ambient Temperature -40°C to +85°C
VCC 2.7V to 3.6V
LEAB X H H L L L L
CLKAB X X X
4. 5. 6. 7.
On the 74FCT163H501 these pins have bus hold. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-impedance = LOW-to-HIGH Transition Output level before the indicated steady-state input conditions were established. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Operation beyond the limits set for th may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
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CY74FCT163501 CY74FCT163H501
Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC = 2.7V to 3.6V
Parameter VIH VIL VH VIK IIH IIL IOZH IOZL IOS IOFF ICC ICC Description Input HIGH Voltage Input LOW Voltage Input Hysteresis[9] Input Clamp Diode Voltage Input HIGH Current Input LOW Current High Impedance Output Current (Three-State Output pins) High Impedance Output Current (Three-State Output pins) Shor t Circuit Current[10] Power-Off Disable Quiescent Power Supply Current Quiescent Power Supply Current (TTL inputs HIGH) VCC=Min., IIN=18 mA VCC=Max., VI=5.5 VCC=Max., VI=GND VCC=Max., VOUT=5.5V VCC=Max., VOUT=GND VCC=Max., VOUT=GND VCC=0V, VOUT4.5V VIN0.2V, VIN>VCC0.2V VCC=Max. 0.1 2.0 60 135 100 0.7 1.2 ±1 ±1 ±1 ±1 240 ±100 10 30 Test Conditions All Inputs Min. 2.0 Typ.[8] Max. 5.5 0.8 Unit V V mV V µA µA µA µA mA µA µA µA
VIN=VCC0.6V[11] VCC=Max.
Notes: 8. Typical values are at VCC=3.3V, TA = +25°C ambient. 9. This parameter is specified but not tested. 10. Not more than one output should be shor ted at a time. Duration of shor t should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shor ting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 11. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
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CY74FCT163501 CY74FCT163H501
Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter VIH VIL VH VIK IIH IIL IBBH IBBL IBHHO IBHLO IOZH IOZL IOS IOFF ICC ICC Description Input HIGH Voltage Input LOW Voltage Input Hysteresis[9] Input Clamp Diode Voltage Input HIGH Current Input LOW Current Bus Hold Sustain Current on Bus Hold Input
[12]
Test Conditions All Inputs
Min. 2.0
Typ.[8]
Max. VCC 0.8
Unit V V mV V µA µA µA µA
100 VCC=Min., IIN=18 mA VCC=Max., VI=VCC VCC=Max., VI=GND VCC=Min. VI=2.0V VI=0.8V 50 +50 ±500 ±1 ±1 60 135 240 ±100 +40 +350 0.7 1.2 ±100 ±100
Bus Hold Overdrive Current on Bus Hold Input High Impedance Output Current (Three-State Output pins) High Impedance Output Current (Three-State Output pins) Shor t Circuit Current[10] Power-Off Disable Quiescent Power Supply Current Quiescent Power supply Current (TTL inputs HIGH)
[12]
VCC=Max., VI=1.5V VCC=Max., VOUT=VCC VCC=Max., VOUT=GND VCC=Max., VOUT=GND VCC=0V, VOUT4.5V VIN0.2V, VIN>VCC0.2V VCC=Max.
µA µA µA mA µA µA µA
VIN=VCC0.6V[11] VCC=Max.
Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter IODL IODH VOH Description Output LOW Dynamic Current
[10]
Test Conditions VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V VCC=Min., IOH= 0.1 mA VCC=3.0V, IOH= 8 mA VCC=3.0V, IOH= 24 mA
Min. 45 45 VCC0.2 2.4[13] 2.0
Typ.[8]
Max. 180 180
Unit mA mA V
Output HIGH Dynamic Current[10] Output HIGH Voltage
3.0 3.0 0.2 0.3 0.55
V V V
VOL
Output LOW Voltage
VCC=Min., IOL= 0.1mA VCC=Min., IOL= 24 mA
Capacitance[9](TA = +25°C, f = 1.0 MHz)
Parameter CIN COUT Description Input Capacitance Output Capacitance VIN = 0V VOUT = 0V Test Conditions Typ.[8] 4.5 5.5 Max. 6.0 8.0 Unit pF pF
Notes: 12. Pins with bus hold are described in Pin Description. 13. VOH=VCC 0.6V at rated current.
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CY74FCT163501 CY74FCT163H501
Power Supply Characteristics
Sym. ICCD Parameter Dynamic Power Supply Current[15] Test Conditions[14] VCC=Max., Outputs Open OEAB=OEBA=VCC or GND One Input Toggling, 50% Duty Cycle VCC=Max., Outputs Open f0 =10MHz (CLKAB) 50% Duty Cycle OEAB=OEBA=VCC LEAB = GND, One Bit Toggling f1 = 5MHz, 50% Duty Cycle VCC=Max., Outputs Open f0 = 10MHz (CLKAB) 50% Duty Cycle OEAB=OEBA=VCC LEAB=GND Eighteen Bits Toggling f1=2.5MHz, 50% Duty Cycle VIN=VCC or VIN=GND Min. -- Typ.[8] 75 Max. 120 Unit µA/ MHz
IC
Total Power Supply Current[16]
VIN=VCC or VIN=GND VIN=3.4V or VIN=GND VIN=VCC or VIN=GND VIN=3.4V or VIN=GND
-- --
0.8 1.3
1.7 3.2
mA
-- --
3.8 8.5
6.5[17] 20.8[17]
Notes: 14. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 15. This parameter is not directly testable, but is derived for use in Total Power Supply Current. 16. IC= IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC+ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) = Duty Cycle for TTL inputs HIGH DH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 17. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
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