|
Details, datasheet, quote on part number:74HCT11
| |
| Part: | 74HCT11 |
| Category: | Logic => Gates => CMOS/BiCMOS->HC/HCT Family |
| Description: | High Speed CMOS Logic Triple 3-input And Gate |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download 74HCT11 datasheet File size : 35 kB |
| Request For quote: | Find where to buy 74HCT11
|
| |
Datasheet text preview:
CD54/74HC11, CD54/74HCT11
Data sheet acquired from Harris Semiconductor SCHS273A
August 1997 - Revised May 2000
High Speed CMOS Logic Triple 3-Input AND Gate
Description
The 'HC11 and 'HCT11 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family.
Features
· Buffered Inputs
[ /Title (CD54 HCT11 , CD74 HC11, CD74 HCT11 ) /Subject High
· Typical Propagation Delay: 8ns at VCC = 5V, CL = 15pF, TA = 25oC · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC11F CD54HC11F3A CD74HC11E CD74HC11M CD54HCT11F CD54HCT11F3A CD74HCT11E CD74HCT11M NOTES: 1. When ordering, use the entire par t number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC
Pinout
CD54HC11, CD54HCT11 (CERDIP) CD54HCT11, CD74HC11, CD74HCT11 (PDIP, SOIC) TOP VIEW
1A 1 1B 2 2A 3 2B 4 2C 5 2Y 6 GND 7 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2000, Texas Instruments Incorporated
1
CD54/74HC11, CD54/74HCT11 Functional Diagram
1 1A 2 1B 2A 2B 2C 2Y GND 3 4 5 6 7 12 1Y 11 3C 10 3B 9 3A 8 3Y 13 1C 14 VCC
TRUTH TABLE INPUTS nA L L L L H H H H nB L L H H L L H H nC L H L H L H L H OUTPUT nY L L L L L L L H
Logic Symbol
nA
nB
nY
nC
2
CD54/74HC11, CD54/74HCT11
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A CERDIP Package . . . . . . . . . . . . . . . . 130 55 SOIC Package . . . . . . . . . . . . . . . . . . . 180 N/A Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 V V V V V V V V V V V V V V V V V V µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
3
CD54/74HC11, CD54/74HCT11
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4) NOTE: 4. For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II VCC and GND VCC or GND VCC - 2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 -4 4.5 to 5.5 4.5 to 5.5 4.5 4.5 2 4.4 3.98 0.8 2 4.4 3.84 0.8 2 4.4 3.7 0.8 V V V V SYMBOL ICC VI (V) VCC or GND IO (mA) VCC (V) 0 6 MIN 25oC TYP MAX 2 -40oC TO 85oC MIN MAX 20 -55oC TO 125oC MIN MAX 40 UNITS µA
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
-
5.5
-
±0.1
-
±1
-
±1
µA
ICC ICC
-
5.5 4.5 to 5.5
-
100
2 360
-
20 450
-
40 490
µA µA
HCT Input Loading Table
INPUT All UNIT LOADS 0.5
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER HC TYPES Propagation Delay, Input to Output (Figure 1) tPLH, tPHL CL = 50pF 2 4.5 6 Propagation Delay, Data Input to Output Y tPLH, tPHL CL = 15pF 5 8 100 20 17 125 25 21 150 30 26 ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
4
CD54/74HC11, CD54/74HCT11
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER Transition Times (Figure 1) SYMBOL tTLH, tTHL TEST CONDITIONS CL = 50pF VCC (V) 2 4.5 6 Input Capacitance Power Dissipation Capacitance (Notes 5, 6) HCT TYPES Propagation Delay, Input to Output (Figure 2) Propagation Delay, Data Input to Output Y Transition Times (Figure 2) Input Capacitance Power Dissipation Capacitance (Notes 5, 6) NOTES: 5. CPD is used to determine the dynamic power consumption, per gate. 6. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. tPLH, tPHL tPLH, tPHL tTLH, tTHL CI CPD CL = 50pF CL = 15pF CL = 50pF CL = 50pF 4.5 5 4.5 5 11 28 28 15 10 35 19 10 42 22 10 ns ns ns pF pF CI CPD CL = 50pF CL = 15pF 5 25oC MIN TYP 26 MAX 75 15 13 10 -40oC TO 85oC -55oC TO 125oC MIN MAX 95 19 16 10 MIN MAX 110 22 19 10 UNITS ns ns ns pF pF
Test Circuits and Waveforms
tr = 6ns INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tf = 6ns VCC INPUT GND tTHL tr = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% tf = 6ns 3V
GND
tTHL
INVERTING OUTPUT
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
5
|
|
