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Part: 74LVTH322374ZKER
Category:
Logic
-> Flip-Flops
-> D-Type (3-State) Flip-Flops
Description: ti SN74LVTH322374, 3.3-V Abt 32-Bit Edge-triggered D-type Flip-flop With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 74LVTH322374ZKER datasheet File size : 110 kB
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Datasheet text preview:
SN74LVTH322374 3.3 V ABT 32 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS
SCBS754B - MARCH 2002 - REVISED SEPTEMBER 2003
D Member of the Texas Instruments D D D D D
Widebus+ Family Output Ports Have Equivalent 22- Series Resistors, So No External Resistors Are Required Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Supports Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion
GKE OR ZKE PACKAGE (TOP VIEW) 1 2 3 4 5 6
D Bus Hold on Data Inputs Eliminates the D D D D
Need for External Pullup/Pulldown Resistors Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A)
terminal assignments
1 2 1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q8 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q8 3 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 4 1CLK GND VCC GND GND VCC GND 2CLK 3CLK GND VCC GND GND VCC GND 4CLK 5 1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D8 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D8 6 1D2 1D4 1D6 1D8 2D2 2D4 2D6 2D7 3D2 3D4 3D6 3D8 4D2 4D4 4D6 4D7 A B C D E F G H J K L M N P R T 1Q2 1Q4 1Q6 1Q8 2Q2 2Q4 2Q6 2Q7 3Q2 3Q4 3Q6 3Q8 4Q2 4Q4 4Q6 4Q7
A B C D E F G H J K L M N P R T
NC - No internal connection
description/ordering information
ORDERING INFORMATION
TA -40°C to 85°C PACKAGE LFBGA - GKE LFBGA - ZKE (Pb-free) Tape and reel ORDERABLE PART NUMBER SN74LVTH322374KR 74LVTH322374ZKER HW374 TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SCBS754B - MARCH 2002 - REVISED SEPTEMBER 2003
SN74LVTH322374 3.3 V ABT 32 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS
description/ordering information (continued)
The SN74LVTH322374 is a 32-bit edge-triggered D-type flip-flop with 3-state outputs designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive transition of the clock (CLK), the Q outputs of the flip-flop take on the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- series resistors to reduce overshoot and undershoot. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
FUNCTION TABLE (each 8-bit flip-flop) INPUTS OE L L L H CLK H or L X D H L X X OUTPUT Q H L Q0 Z
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74LVTH322374 3.3 V ABT 32 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS
SCBS754B - MARCH 2002 - REVISED SEPTEMBER 2003
logic diagram (positive logic)
1OE 1CLK A3 A4 C1 1D A2 2OE 2CLK 1Q1 H3 H4 C1 2D1 E5 1D E2
1D1
A5
2Q1
To Seven Other Channels J3 J4 C1 1D J2 T3 T4
To Seven Other Channels
3OE 3CLK
4OE 4CLK 3Q1
C1 4D1 N5 1D
3D1
J5
N2
4Q1
To Seven Other Channels
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 3): GKE/ZKE package . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SCBS754B - MARCH 2002 - REVISED SEPTEMBER 2003
SN74LVTH322374 3.3 V ABT 32 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS
recommended operating conditions (see Note 4)
MIN VCC VIH VIL VI IOH IOL t/v t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate Outputs enabled 200 2.7 2 0.8 5.5 -12 12 10 MAX 3.6 UNIT V V V V mA mA ns/V µs/V
TA Operating free-air temperature -40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL Control inputs II Data inputs Ioff VCC = 2.7 V, VCC = 3 V, VCC = 3 V, VCC = 0 or 3.6 V, VCC = 3.6 V, VCC = 3.6 V VCC = 0, VCC = 3 V II(hold) Data inputs VCC = 3.6 V, IOZH IOZL IOZPU IOZPD ICC VCC = 3.6 V, VCC = 3.6 V, TEST CONDITIONS II = -18 mA IOH = -12 mA IOL = 12 mA VI = 5.5 V VI = VCC or GND VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V VO = 3 V VO = 0.5 V 75 -75 500 -750 5 -5 ±100 ±100 0.38 10 0.38 0.2 3 9 mA pF mA µA MIN 2 0.8 10 ±1 1 -5 ±100 µA µA TYP MAX -1.2 UNIT V V V
µA µA µA µA
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care Outputs high VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs low Outputs disabled
ICC§ Ci Co
VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND VI = 3 V or 0 VO = 3 V or 0
pF All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74LVTH322374 3.3 V ABT 32 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS
SCBS754B - MARCH 2002 - REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V ± 0.3 V MIN fclock tw tsu th Clock frequency Pulse duration, CLK high or low Setup time, data before CLK Hold time, data after CLK High or low High or low 3 1.8 0.8 MAX 160 3 2 0.1 VCC = 2.7 V MIN MAX 160 MHz ns ns ns UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN 160 2 CLK OE OE Q Q Q 2.2 1.8 1.8 2.4 2 3.4 3.3 3.5 3.5 4.2 3.8 5.3 4.9 5.6 4.9 5.4 5 0.5 TYP MAX VCC = 2.7 V MIN 160 6.2 5.1 6.9 6 5.7 5.1 ns ns ns ns MAX MHz UNIT
tsk(o) All typical values are at VCC = 3.3 V, TA = 25°C.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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