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Part: 80021012A
Category:
Logic
-> Transceivers
-> Standard Transceivers
Description: ti SN54LS245, Octal Bus Transceivers With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 80021012A datasheet File size : 252 kB
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SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SDLS146A OCTOBER 1976 REVISED FEBRUARY 2002
D D D D
3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns
IOL (SINK CURRENT) 12 mA 24 mA IOH (SOURCE CURRENT) 12 mA 15 mA
SN54LS245 . . . J OR W PACKAGE SN74LS245 . . . DB, DW, N, OR NS PACKAGE (TOP VIEW)
TYPE SN54LS245 SN74LS245
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC OE B1 B2 B3 B4 B5 B6 B7 B8
description
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can disable the device so that the buses are effectively isolated.
SN54LS245 . . . FK PACKAGE (TOP VIEW)
A2 A1 DIR VCC OE A3 A4 A5 A6 A7
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
B1 B2 B3 B4 B5
ORDERING INFORMATION
TA PDIP N 0°C to 70°C SOIC DW DW SOP NS SSOP DB CDIP J 55°C to 125°C to 125°C CFP W LCCC FK PACKAGE Tube Tube Tape and reel Tape and reel Tape and reel Tube Tube Tube Tube ORDERABLE PART NUMBER SN74LS245N SN74LS245DW SN74LS245DWR SN74LS245NSR SN74LS245DBR SN54LS245J SNJ54LS245J SNJ54LS245W SN54LS245FK 74LS245 LS245 SN54LS245J SNJ54LS245J SNJ54LS245W TOP-SIDE MARKING SN74LS245N LS245
SN54LS245FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
A8 GND B8 B7 B6
1
SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SDLS146A OCTOBER 1976 REVISED FEBRUARY 2002
FUNCTION TABLE INPUTS OE L L H DIR L H X OPERATION B data to A bus A data to B bus Isolation
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT VCC 9 k NOM 50 NOM TYPICAL OF ALL OUTPUTS VCC
Input Output
logic diagram (positive logic)
DIR 1 19
OE
A1
2
18
B1
To Seven Other Channels
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SDLS146A OCTOBER 1976 REVISED FEBRUARY 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, qJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54LS245 MIN VCC IOH IOL TA Supply voltage High-level output current Low-level output current Operating free-air temperature 55 4.5 NOM 5 MAX 5.5 12 12 125 0 SN74LS245 UNIT MIN 4.75 NOM 5 MAX 5.25 15 24 70 V mA mA °C
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SDLS146A OCTOBER 1976 REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIH VIL VIK High-level input voltage Low-level input voltage Input clamp voltage Hysteresis (VT+ VT) VOH High-level output voltage output voltage A or B VCC = MIN, VCC = MIN VCC = MIN, VIH = 2 V V, VIL = VIL(max) VCC = MIN, VIH = 2 V V, VIL = VIL(max) VCC = MAX, OE at 2 V VCC = MAX, OE at 2 V VCC = MAX MAX VCC = MAX, VCC = MAX, VCC = MAX VCC = MAX Outputs open II = 18 mA 0.2 IOH = 3 mA IOH = MAX IOL = 12 mA IOL = 24 mA VO = 2.7 V VO = 0.4 V VI = 5.5 V VI = 7 V VIH = 2.7 V VIL = 0.4 V 40 48 62 64 20 200 0.1 0.1 20 0.2 225 70 90 95 40 48 62 64 2.4 2 0.4 0.4 3.4 TEST CONDITIONS CONDITIONS SN54LS245 MIN 2 0.7 1.5 0.2 2.4 2 0.4 V 0.5 20 200 0.1 mA 0.1 20 0.2 225 70 90 95 mA µA mA mA µA µA 0.4 3.4 V TYP MAX SN74LS245 MIN 2 0.8 1.5 TYP MAX UNIT V V V V
VOL
Low-level output voltage output voltage Off-state output current, high-level voltage applied Off-state output current, low-level voltage applied Input current at maximum input input voltage A or B DIR or OE
IOZH IOZL II IIH IIL IOS ICC
High-level input current Low-level input current Short-circuit output current§ Total, outputs high Supply current Total, outputs low Outputs at high Z
For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions. All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
PARAMETER tPLH tPHL tPZL tPZH tPLZ tPHZ Propagation delay time, low- to high-level output Propagation delay time high to low level output delay time, high- to low-level output Output enable time to low level Output enable time to high level Output disable time from low level Output disable time from high level CL = 45 pF 45 pF, CL = 45 pF 45 pF, CL = 5 pF pF, TEST CONDITIONS RL = 667 W 667 RL = 667 W 667 RL = 667 W 667 MIN TYP 8 8 27 25 15 15 MAX 12 12 40 40 25 28 ns UNIT
ns ns
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SDLS146A OCTOBER 1976 REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES
VCC Test Point VCC VCC RL From Output Under Test CL (see Note A) RL (see Note B) From Output Under Test CL (see Note A) Test Point S2 Test Point RL S1 (see Note B) 5 k
From Output Under Test CL (see Note A)
LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS High-Level Pulse
LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS Timing Input tsu 1.3 V Data Input 1.3 V
LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V 1.3 V 0V th 3V 1.3 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
1.3 V tw
1.3 V
Low-Level Pulse
1.3 V
VOLTAGE WAVEFORMS PULSE DURATIONS Output Control (low-level enabling) tPZL Waveform 1 (see Notes C and D) tPZH VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Waveform 2 (see Notes C and D)
3V 1.3 V 1.3 V 0V tPLZ 1.5 V VOL + 0.5 V VOL tPHZ VOH 1.3 V VOH 0.5 V 1.5 V
3V Input 1.3 V 1.3 V 0V tPLH In-Phase Output (see Note D) tPHL Out-of-Phase Output (see Note D) 1.3 V tPHL VOH 1.3 V VOL tPLH
1.3 V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 , tr 1.5 ns, tf 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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