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Part: 8413601SA
Category:
Logic
-> Flip-Flops
-> D-Type Flip-Flops
Description: ti SN54ALS273, Octal D-type Flip-flops With Clear
Company: Texas Instruments, Inc.
Datasheet: Download 8413601SA datasheet File size : 79 kB
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Datasheet text preview:
SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
SDAS218A APRIL 1982 REVISED DECEMBER 1994
· · · · ·
Contain Eight Flip-Flops With Single-Rail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54ALS273 . . . J PACKAGE SN74ALS273 . . . DW OR N PACKAGE (TOP VIEW)
CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK
description
These octal positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct-clear (CLR) input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input signal has no effect at the output. The SN54ALS273 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ALS273 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE (each flip-flop) INPUTS CLR L H H H CLK X H or L D X H L X OUTPUT Q L H L Q0 SN54ALS273 . . . FK PACKAGE (TOP VIEW)
1D 1Q CLR VCC
2D 2Q 3Q 3D 4D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
8Q 8D 7D 7Q 6Q 6D
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1994, Texas Instruments Incorporated
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4Q GND CLK 5Q 5D
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SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
SDAS218A APRIL 1982 REVISED DECEMBER 1994
logic symbol
CLR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 11 3 4 7 8 13 14 17 18 R C1 1D 2 5 6 9 12 15 16 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1D CLK 11 3 2D 4 3D 7 4D 8 5D 13 6D 14 7D 17 8D 18
1D C1 R CLR 1 2 1Q
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
1D C1 R
5 2Q
6 3Q
9 4Q
12 5Q
15 6Q
16 7Q
19 8Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 125°C SN74ALS273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
SDAS218A APRIL 1982 REVISED DECEMBER 1994
recommended operating conditions
SN54ALS273 MIN VCC VIH VIL IOH IOL fclock tw Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Clock frequency CLR low Pulse duration CLK high CLK low tsu th TA Setup time before CLK time before CLK Hold time, data after CLK Operating free-air temperature Data CLR inactive state 0 10 16.5 16.5 10 15 0 55 125 4.5 2 0.7 1 12 30 0 10 14 14 10 15 0 0 70 ns ns °C ns NOM 5 MAX 5.5 SN74ALS273 MIN 4.5 2 0.8 2.6 24 35 NOM 5 MAX 5.5 UNIT V V V mA mA MHz
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH TEST CONDITIONS CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4 5 V 4.5 VCC = 4 5 V 4.5 VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V VCC = 5.5 V II = 18 mA IOH = 0.4 mA IOH = 1 mA IOH = 2.6 mA IOL = 12 mA IOL = 24 mA VI = 7 V VI = 2.7 V VI = 0.4 V VO = 2.25 V 20 11 19 SN54ALS273 MIN TYP MAX 1.5 VCC 2 2.4 VCC 2 3.3 2.4 0.25 0.4 0.1 20 0.2 112 20 29 30 11 19 3.2 0.25 0.35 0.4 0.5 0.1 20 0.2 112 20 29 V mA µA mA mA mA V SN74ALS273 MIN TYP MAX 1.5 UNIT V
VOL II IIH IIL IO ICCH ICCL
mA All typical values are at VCC = 5 V, TA = 25°C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
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3
SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
SDAS218A APRIL 1982 REVISED DECEMBER 1994
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 , TA = MIN to MAX SN54ALS273 SN74ALS273 MIN fmax tPHL tPLH tPHL 30 CLR CLK Any Q Any Q 4 2 3 24 20 17 MAX MIN 35 4 2 3 18 12 15 MAX MHz ns ns
PARAMETER
FROM (INPUT)
TO (OUTPUT)
UNIT
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
SDAS218A APRIL 1982 REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V VCC S1 RL From Output Under Test CL (see Note A) RL Test Point R1 From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) R2 Test Point RL = R1 = R2
LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR 3-STATE OUTPUTS
Timing Input tsu Data Input 1.3 V
3.5 V 1.3 V 0.3 V th 3.5 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
High-Level Pulse
3.5 V 1.3 V tw 1.3 V 0.3 V
Low-Level Pulse
3.5 V 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATIONS
Output Control (low-level enabling) tPZL Waveform 1 S1 Closed (see Note B)
3.5 V 1.3 V 1.3 V 0.3 V tPLZ 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V 3.5 V Input tPLH In-Phase Output 1.3 V 1.3 V 1.3 V 0.3 V tPHL VOH 1.3 V VOL tPLH VOH 1.3 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V VOL
[3.5 V
tPHZ tPZH Waveform 2 S1 Open (see Note B)
tPHL Out-of-Phase Output (see Note C)
[0 V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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