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Part: 84150012A
Category:
Logic
-> Flip-Flops
-> D-Type Flip-Flops
Description: ti SN54HC109, Dual J-k Positive-edge-triggered Flip-flops With Clear And Preset
Company: Texas Instruments, Inc.
Datasheet: Download 84150012A datasheet File size : 79 kB
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Datasheet text preview:
SN54HC109, SN74HC109 DUAL J K POSITIVE EDGE TRIGGERED FLIP FLOPS WITH CLEAR AND PRESET
SCLS470A - MARCH 2003 - REVISED OCTOBER 2003
D Wide Operating Voltage Range of 2 V to 6 V D Low Input Current of 1 µA Max D High-Current Outputs Drive Up To
10 LSTTL Loads
SN54HC109 . . . J OR W PACKAGE SN74HC109 . . . D, N, OR NS PACKAGE (TOP VIEW)
D Low Power Consumption, 40-µA Max ICC D Typical tpd = 12 ns D ±4-mA Output Drive at 5 V
SN54HC109 . . . FK PACKAGE (TOP VIEW)
1J 1C LR NC VCC 1K 1CLK NC 1PRE 1Q
3 4 5 6 7 8
1CLR 1J 1K 1CLK 1PRE 1Q 1Q GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 2CLR 2J 2K 2CLK 2PRE 2Q 2Q
2 1 20 19 18 17 16 15
2C LR 2J 2K NC 2CLK 2PRE
14 9 10 11 12 13
NC - No internal connection
description/ordering information
These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. ORDERING INFORMATION
TA PDIP - N -40°C to 85 C 85°C PACKAGE Tube of 25 Tube of 40 SOIC - D SOP - NS CDIP - J -55°C to 125 C 125°C CFP - W LCCC - FK Reel of 2500 Reel of 250 Reel of 2000 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74HC109N SN74HC109D SN74HC109DR SN74HC109DT SN74HC109NSR SNJ54HC109J SNJ54HC109W SNJ54HC109FK HC109 SNJ54HC109J SNJ54HC109W HC109 TOP-SIDE MARKING SN74HC109N
SNJ54HC109FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1Q GND NC 2Q 2Q
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
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SCLS470A - MARCH 2003 - REVISED OCTOBER 2003
SN54HC109, SN74HC109 DUAL J K POSITIVE EDGE TRIGGERED FLIP FLOPS WITH CLEAR AND PRESET
FUNCTION TABLE INPUTS PRE L H L H H H H CLR H L L H H H H CLK X X X J X X X L H L H K X X X L L H H H OUTPUTS Q H L H L Toggle Q0 Q0 L Q L H H H
H H L X X Q0 Q0 This configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level.
logic diagram, each flip-flop (positive logic)
PRE C C TG TG K C C C CLK C TG C C CLR C Q TG C Q
J
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC109, SN74HC109 DUAL J K POSITIVE EDGE TRIGGERED FLIP FLOPS WITH CLEAR AND PRESET
SCLS470A - MARCH 2003 - REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, JA (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: FK, J, or W packages . . . . . . . . . . . 300°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or NS packages . . . . . . . . . . . 260°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
SN54HC109 MIN VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage Input voltage Output voltage VCC = 2 V VCC = 4.5 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.3 0.9 1.2 VCC VCC 1000 500 0 0 NOM 5 MAX 6 SN74HC109 MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 ns V V V V NOM 5 MAX 6 UNIT V
High-level input voltage
Input transition rise/fall time
VCC = 6 V 400 400 TA Operating free-air temperature -55 125 -40 85 °C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
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3
SCLS470A - MARCH 2003 - REVISED OCTOBER 2003
SN54HC109, SN74HC109 DUAL J K POSITIVE EDGE TRIGGERED FLIP FLOPS WITH CLEAR AND PRESET
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = -20 µA VOH VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 MIN 1.9 4.4 5.9 3.98 5.48 TA = 25°C TYP MAX 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 ±0.1 0.1 0.1 0.1 0.26 0.26 ±100 4 10 SN54HC109 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1000 80 10 MAX SN74HC109 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1000 40 10 nA µA pF V V MAX UNIT
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 2V fclock Clock frequency 4.5 V 6V 2V PRE or CLR low tw Pulse duration CLK high or low 4.5 V 6V 2V 4.5 V 6V 2V Data (J, K) tsu Setup time before CLK PRE or CLR inactive 4.5 V 6V 2V 4.5 V 6V 2V th Hold time Data after CLK CLK 4.5 V 6V 100 20 17 80 16 14 100 20 17 25 5 4 0 0 0 TA = 25°C MIN MAX 6 31 36 150 30 25 120 24 20 150 30 25 40 8 7 0 0 0 SN54HC109 MIN MAX 4.2 21 25 125 25 21 100 20 17 125 25 21 30 6 5 0 0 0 ns ns ns SN74HC109 MIN MAX 5 25 29 MHz UNIT
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC109, SN74HC109 DUAL J K POSITIVE EDGE TRIGGERED FLIP FLOPS WITH CLEAR AND PRESET
SCLS470A - MARCH 2003 - REVISED OCTOBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V PRE or CLR tpd CLK Q or Q Q or Q 4.5 V 6V 2V 4.5 V 6V 2V tt Q or Q 4.5 V 6V MIN 6 31 36 TA = 25°C TYP MAX 10 50 60 60 15 12 50 15 12 28 8 6 230 46 39 175 35 30 75 15 13 SN54HC109 MIN 4.2 21 25 345 69 59 250 50 42 110 22 19 MAX SN74HC109 MIN 5 25 29 290 58 49 220 44 37 95 19 16 ns ns ns MAX UNIT
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per buffer/driver TEST CONDITIONS No load TYP 35 UNIT pF
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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