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Part: 8415001EA
Category:
Logic
-> Flip-Flops
Description: ti CD54HC109, High Speed CMOS Logic Dual Positive-edge Trigger J-k Flip-flops With Set And Reset
Company: Texas Instruments, Inc.
Datasheet: Download 8415001EA datasheet File size : 79 kB
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Datasheet text preview:
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
Data sheet acquired from Harris Semiconductor SCHS140E
March 1998 - Revised October 2003
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
Description
The 'HC109 and 'HCT109 are dual J-K flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP). The flip-flop is set and reset by active-low S and R, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.
Features
· Asynchronous Set and Reset
[ /Title (CD74H C109, CD74H CT109) /Subject (Dual JK FlipFlop with Set and Reset
· Schmitt Trigger Clock Inputs · Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC109F3A CD54HCT109F3A CD74HC109E CD74HC109M CD74HC109MT CD74HC109M96 CD74HCT109E CD74HCT109M CD74HCT109MT CD74HCT109M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Pinout
CD54HC109, CD54HCT109 (CERDIP) CD74HC109, CD74HCT109 (PDIP, SOIC) TOP VIEW
1R 1 1J 2 1K 3 1CP 4 1S 5 1Q 6 1Q 7 GND 8 16 VCC 15 2R 14 2J 13 2K 12 2CP 11 2S 10 2Q 9 2Q
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Functional Diagram
1S 1J 1K 1CP 1R 5 2 3 4 1 F/F 1
6 1Q 7 1Q
2S 2J 2K 2CP 2R
11 14 13 12 15 F/F 2 10 2Q 9 2Q GND = 8 VCC = 16
TRUTH TABLE INPUTS S L H L H H H H H R H L L H H H H H CP X X X J X X X L H L H X K X X X L L H H X H No Change Q H L H (Note 1) L Toggle No Change L OUTPUTS Q L H H (Note 1) H
L
H= High Level (Steady State) L= Low Level (Steady State) X= Don't Care = Low-to-High Transition NOTE: 1. Unpredictable and unstable condition if both S and R go high simultaneously
Logic Diagram
5(11) S 2(14) J 3(13) K 4(12) CP 1(15) R 16 VCC GND 8 6(10) Q 7(9) Q
JS FF K CL CL
Q
RQ
2
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC CP Input Rise and Fall Time, tr, tf 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) Input Rise and Fall Time (All Inputs Except CP), tr, tf 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads VOH VIH or VIL -0.02 2 4.5 6 -4 -5.2 4.5 6 1.5 3.15 4.2 1.9 4.4 5.9 3.96 5.48 0.5 1.35 1.8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 V V V V V V V V V V V V SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II VCC and GND VCC or GND VCC - 2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V II ICC VCC or GND VCC or GND SYMBOL VOL VI (V) VIH or VIL IO (mA) VCC (V) 0.02 2 4.5 6 4 5.2 0 4.5 6 6 6 MIN 25oC TYP MAX 0.1 0.1 0.1 0.26 0.26 ±0.1 4 -40oC TO 85oC MIN MAX 0.1 0.1 0.1 0.33 0.33 ±1 40 -55oC TO 125oC MIN MAX 0.1 0.1 0.1 0.4 0.4 ±1 80 UNITS V V V V V V µA µA
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02 4
4.5 4.5
-
-
0.1 0.26
-
0.1 0.33
-
0.1 0.4
V V
-
5.5
-
±0.1
-
±1
-
±1
µA
ICC ICC (Note 3)
0 -
5.5 4.5 to 5.5
-
100
4 360
-
40 450
-
80 490
µA µA
HCT Input Loading Table
INPUT All UNIT LOADS 0.3
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
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CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
Prerequisite For Switching Specifications
PARAMETER HC TYPES Setup Time J, K, to CP tSU 2 4.5 6 Hold Time J, K, to CP tH 2 4.5 6 Removal Time R, S, to CP tREM 2 4.5 6 Pulse Width CP, R, S tW 2 4.5 6 CP Frequency fMAX 2 4.5 6 HCT TYPES Setup Time J, K to CP Hold Time J, K to CP Removal Time R, S, to CP Pulse Width CP, R, S CP Frequency tSU tH tREM tW fMAX 4.5 4.5 4.5 4.5 4.5 18 3 18 18 27 23 3 23 23 22 27 3 27 27 18 ns ns ns ns MHz 80 16 14 5 5 5 80 16 14 80 16 14 6 30 35 100 20 17 5 5 5 100 20 17 100 20 17 5 25 29 120 24 20 5 5 5 120 24 20 120 24 20 4 20 23 ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
Switching Specifications Input tr, tf = 6ns
PARAMETER HC TYPES Propagation Delay, CP Q, Q tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF Propagation Delay, SQ tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF Propagation Delay, SQ tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF 2 4.5 5 6 2 4.5 5 6 2 4.5 5 6 14 9 13 175 35 30 120 24 20 155 31 26 220 44 37 150 30 26 195 39 33 265 53 45 180 36 31 235 47 40 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
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Others parts begin by 84
84-1 84-2
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