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Details, datasheet, quote on part number:8500101EA
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| Part: | 8500101EA |
| Category: | Logic => Buffers/Drivers => Non-Inverting Buffers and Drivers |
| Description: | ti CD54HC365, High Speed CMOS Logic Non-inverting Hex Buffer/line Driver With 3-State Outputs |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download 8500101EA datasheet File size : 166 kB |
| Request For quote: | Find where to buy 8500101EA
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Datasheet text preview:
CD54/74HC365, CD54/74HCT365, CD54/74HC366
Data sheet acquired from Harris Semiconductor SCHS180C
November 1997 - Revised October 2003
High Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting
low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs. The 'HC365 and 'HCT365 are non-inverting buffers, whereas the 'HC366 is an inverting buffer. These devices have two three-state control inputs (OE1 and OE2) which are NORed together to control all six gates. The 'HCT365 logic families are speed, function and pin compatible with the standard LS logic family.
Features
· Buffered Inputs
[ /Title (CD74 HC365 , CD74 HCT36 5, CD74 HC366 , CD74 HCT36 6) /Subject (High Speed
· High Current Bus Driver Outputs · Typical Propagation Delay tPLH, tPHL = 8ns at VCC = 5V, CL = 15pF, TA = 25oC · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC365F3A CD54HC366F3A CD54HCT365F3A CD74HC365E CD74HC365M CD74HC365MT CD74HC365M96 CD74HC366E CD74HC366M CD74HC366M96 CD74HCT365E CD74HCT365M CD74HCT365MT CD74HCT365M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Description
The 'HC365, 'HCT365, and 'HC366 silicon gate CMOS threestate buffers are general purpose high-speed non-inverting and inverting buffers. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and real. The suffix T denotes a small-quantity reel of 250.
Pinout
CD54HC365, CD54HCT365, CD54HC366 (CERDIP) CD74HC365, CD74HCT365, CD74HC366 (PDIP, SOIC) TOP VIEW
OE1 1 1A 2 (1Y) 1Y 3 2A 4 (2Y) 2Y 5 3A 6 (3Y) 3Y 7 GND 8 16 VCC 15 OE2 14 6A 13 6Y (6Y) 12 5A 11 5Y (5Y) 10 4A 9 4Y (4Y)
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
1
CD54/74HC365, CD54/74HCT365, CD54/74HC366 Functional Diagrams
HC365, HCT365
1
HC366
OE1
1
16
VCC
OE1
16
VCC
1A
2 3
15 14
OE2 6A
1A
2 3
15 14
OE2 6A
1Y
1Y
2A
4
13
6Y
2A
4
13
6Y
2Y
5 6
12
5A
2Y
5 6
12
5A
3A 7
11 10
5Y
3A 7
11 10
5Y
3Y
4A 9
3Y
4A 9
GND
8
4Y
GND
8
4Y
TRUTH TABLE OUTPUTS (Y) A L H X X HC/HCT365 L H Z Z HC366 H L Z
INPUTS OE1 L L X H OE2 L L H X
NOTE: H = High Voltage Level L = Low Voltage Level X = Don't Care Z = High Impedance (OFF) State
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CD54/74HC365, CD54/74HCT365, CD54/74HC366 Logic Diagram
VCC 16 ONE OF SIX IDENTICAL CIRCUITS 2 1A 3 1Y
(NOTE)
GND 8
1 OE1 4 15 OE2 6 3A 10 4A 12 5A 14 6A 7 3Y 9 4Y 11 5Y 2A 5 2Y
13 6Y
NOTE: Inver ter not included in HC/HCT365. FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT365 AND HC366 (OUTPUTS FOR HC/HCT365 ARE COMPLEMENTS OF THOSE SHOWN, i.e., 1Y, 2Y, ETC.)
3
CD54/74HC365, CD54/74HCT365, CD54/74HC366
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -6 -7.8 0.02 0.02 0.02 6 7.8 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54/74HC365, CD54/74HCT365, CD54/74HC366
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Three-State Leakage Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 2) Three-State Leakage Current NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC VCC to GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL IOZ VI (V) VIL or VIH IO (mA) VCC (V) VO = VCC or GND 6 MIN 25oC TYP MAX ±0.5 -40oC TO 85oC MIN MAX ±5.0 -55oC TO 125oC MIN MAX ±10 UNITS µA
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
IOZ
VIL or VIH
VO = VCC or GND
5.5
-
-
±0.5
-
±5.0
-
±10
µA
HCT Input Loading Table
INPUT OE1 All Others UNIT LOADS 0.6 0.55
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
Switching Specifications - HC/HCT365 Input tr, tf = 6ns
TEST CONDITIONS 25oC VCC (V) 2 4.5 6 CL = 15pF 5 TYP MAX -40oC TO 85oC MAX -55oC TO 125oC MAX UNITS
PARAMETER HC TYPES Propagation Delay, Data to Outputs HC/HCT365
SYMBOL
tPLH, tPHL
CL = 50pF
8
105 21 18 -
130 26 22 -
160 32 27 -
ns ns ns ns
5
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