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Part: 85003012A
Category:
Logic
-> Counters
-> Binary Counters
Description: ti SN54HC4020, Asynchronous 14-Bit Binary Counters
Company: Texas Instruments, Inc.
Datasheet: Download 85003012A datasheet File size : 44 kB
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SN54HC4020, SN74HC4020 14 BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158E - DECEMBER 1982 - REVISED SEPTEMBER 2003
D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC
SN54HC4020 . . . J OR W PACKAGE SN74HC4020 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
D Typical tpd = 12 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max
SN54HC4020 . . . FK PACKAGE (TOP VIEW)
NC - No internal connection
description/ordering information
The 'HC4020 devices are 14-stage binary ripple-carry counters that advance on the negative-going edge of the clock pulse. The counters are reset to zero (all outputs low) independently of the clock (CLK) input when the clear (CLR) input goes high. ORDERING INFORMATION
TA PDIP - N PACKAGE Tube of 25 Tube of 40 SOIC - D -40°C to 85 C 85°C SOP - NS SSOP - DB Reel of 2500 Reel of 250 Reel of 2000 Reel of 2000 Tube of 90 TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W LCCC - FK Reel of 2000 Reel of 250 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74HC4020N SN74HC4020D SN74HC4020DR SN74HC4020DT SN74HC4020NSR SN74HC4020DBR SN74HC4020PW SN74HC4020PWR SN74HC4020PWT SNJ54HC4020J SNJ54HC4020W SNJ54HC4020FK SNJ54HC4020J SNJ54HC4020W HC4020 HC4020 HC4020 HC4020 TOP-SIDE MARKING SN74HC4020N
SNJ54HC4020FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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QD GND NC QA CLK
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
QL QM QN QF QE QG QD GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC QK QJ QH QI CLR CLK QA
QN QF NC QE QG
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
NC VCC QK QJ QH NC QI CLR
QM QL
Copyright 2003, Texas Instruments Incorporated
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SN54HC4020, SN74HC4020 14 BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158E - DECEMBER 1982 - REVISED SEPTEMBER 2003
FUNCTION TABLE (each buffer) INPUTS CLK X CLR L L H FUNCTION No change Advance to next stage All outputs L
logic diagram (positive logic)
CLR 11
R CLK 10 T
R T
R T
R T
R T
R T
9 QA
7 QD
5 QE
4 QF
R T
R T
R T
R T
R T
R T
R T
R T
6 QG
13 QH
12 QI
14 QJ
15 QK
1 QL
2 QM
3 QN
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC4020, SN74HC4020 14 BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158E - DECEMBER 1982 - REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
SN54HC4020 MIN VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage Input voltage Output voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 0 0 NOM 5 MAX 6 SN74HC4020 MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 ns V V V V NOM 5 MAX 6 UNIT V
High-level input voltage
Input transition rise/fall time
TA Operating free-air temperature -55 125 -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = -20 µA VOH VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 TA = 25°C MIN TYP MAX 1.9 4.4 5.9 3.98 5.48 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 ±0.1 0.1 0.1 0.1 0.26 0.26 ±100 8 10 SN54HC4020 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1000 160 10 MAX SN74HC4020 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1000 80 10 nA µA pF V V MAX UNIT
POST OFFICE BOX 655303
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3
SN54HC4020, SN74HC4020 14 BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158E - DECEMBER 1982 - REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 2V fclock Clock frequency 4.5 V 6V 2V CLK high or low tw Pulse duration CLR high 4.5 V 6V 2V 4.5 V 6V 2V tsu Setup time, CLR inactive before CLK 4.5 V 6V 90 18 15 70 14 12 60 12 10 TA = 25°C MIN MAX 5.5 28 33 135 27 23 105 21 18 90 18 15 SN54HC4020 MIN MAX 3.7 19 22 115 23 20 90 18 25 75 15 13 ns ns SN74HC4020 MIN MAX 4.3 22 25 MHz UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V tpd CLK QA 4.5 V 6V 2V tPHL CLR Any 4.5 V 6V 2V tt Any 4.5 V 6V TA = 25°C MIN TYP MAX 5.5 28 33 10 45 53 62 16 12 63 17 13 28 8 6 150 30 26 140 28 24 75 15 13 SN54HC4020 MIN 3.7 19 22 225 45 38 210 42 36 110 22 19 MAX SN74HC4020 MIN 4.3 22 25 190 38 32 175 35 30 95 19 16 ns ns ns MHz MAX UNIT
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP 88 UNIT pF
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC4020, SN74HC4020 14 BIT ASYNCHRONOUS BINARY COUNTERS
SCLS158E - DECEMBER 1982 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
From Output Under Test Test Point CL = 50 pF (see Note A) LOAD CIRCUIT VCC 50% tPLH In-Phase Output 50% 10% tPHL Out-of-Phase Output 90% 50% 10% tf 90% tr tPLH 50% 10% 90% tr 50% 0V tPHL 90% VOH 50% 10% VOL tf VOH VOL Low-Level Pulse 50% Data Input 50% 10% Reference Input tsu 90% 90% VCC 50% 10% 0 V tf 50% VCC 0V
tr
Input
VOLTAGE WAVEFORMS SETUP AND INPUT RISE AND FALL TIMES
High-Level Pulse
VCC 50% tw VCC 50% 0V VOLTAGE WAVEFORMS PULSE DURATIONS 50% 0V
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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