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Details, datasheet, quote on part number:8512801RA
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| Part: | 8512801RA |
| Category: | Logic => Latches => D-Type (3-State) Latches |
| Description: | ti SN54HC573A, Octal D-type Transparent Latches With 3-State Outputs |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download 8512801RA datasheet File size : 324 kB |
| Request For quote: | Find where to buy 8512801RA
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Datasheet text preview:
SN54HC573A, SN74HC573A OCTAL TRANSPARENT D TYPE LATCHES WITH 3 STATE OUTPUTS
SCLS147E - DECEMBER 1982 - REVISED SEPTEMBER 2003
D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State Outputs Drive Bus
Lines Directly or Up To 15 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
SN54HC573A . . . J OR W PACKAGE SN74HC573A . . . DB, DW, N, OR PW PACKAGE (TOP VIEW)
D D D D
Typical tpd = 21 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Bus-Structured Pinout
SN54HC573A . . . FK PACKAGE (TOP VIEW)
OE 1D 2D 3D 4D 5D 6D 7D 8D GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE
3D 4D 5D 6D 7D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
OE VCC 1Q 2Q 3Q 4Q 5Q 6Q
TOP-SIDE MARKING SN74HC573AN HC573A HC573A HC573A SNJ54HC573AJ SNJ54HC573AW
description/ordering information
These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. ORDERING INFORMATION
TA PDIP - N SOIC - DW -40°C to 85°C SSOP - DB TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W LCCC - FK PACKAGE Tube of 25 Tube of 40 Reel of 2500 Reel of 2000 Reel of 2000 Reel of 250 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74HC573AN SN74HC573ADW SN74HC573ADWR SN74HC573ADBR SN74HC573APWR SN74HC573APWT SNJ54HC573AJ SNJ54HC573AW SNJ54HC573AFK
SNJ54HC573AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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8D GND LE 8Q 7Q
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
2D 1D
Copyright 2003, Texas Instruments Incorporated
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SCLS147E - DECEMBER 1982 - REVISED SEPTEMBER 2003
SN54HC573A, SN74HC573A OCTAL TRANSPARENT D TYPE LATCHES WITH 3 STATE OUTPUTS
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z
logic diagram (positive logic)
OE LE 1 11
C1 1D 2 1D
19
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303
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SN54HC573A, SN74HC573A OCTAL TRANSPARENT D TYPE LATCHES WITH 3 STATE OUTPUTS
SCLS147E - DECEMBER 1982 - REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
SN54HC573A MIN VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO tt Low-level input voltage Input voltage Output voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 0 0 NOM 5 MAX 6 SN74HC573A MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 ns V V V V NOM 5 MAX 6 UNIT V
High-level input voltage
Input transition (rise and fall) time
TA Operating free-air temperature -55 125 -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = -20 µA VOH VI = VIH or VIL IOH = -6 mA IOH = -7.8 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 6 mA IOL = 7.8 mA II IOZ ICC Ci VI = VCC or 0 VO = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 6V 2 V to 6 V 3 TA = 25°C MIN TYP MAX 1.9 4.4 5.9 3.98 5.48 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 ±0.1 ±0.01 0.1 0.1 0.1 0.26 0.26 ±100 ±0.5 8 10 SN54HC573A MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1000 ±10 160 10 MAX SN74HC573A MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1000 ±5 80 10 nA µA µA pF V V MAX UNIT
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3
SCLS147E - DECEMBER 1982 - REVISED SEPTEMBER 2003
SN54HC573A, SN74HC573A OCTAL TRANSPARENT D TYPE LATCHES WITH 3 STATE OUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 2V tw Pulse duration, LE high 4.5 V 6V 2V tsu Setup time, data before LE 4.5 V 6V 2V th Hold time, data after LE 4.5 V 6V TA = 25°C MIN MAX 80 16 14 50 10 9 20 5 5 SN54HC573A MIN 120 24 20 75 15 13 24 5 5 MAX SN74HC573A MIN 100 20 17 63 13 11 24 5 5 ns ns ns MAX UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V D tpd LE Any Q Q 4.5 V 6V 2V 4.5 V 6V 2V ten OE Any Q 4.5 V 6V 2V tdis OE Any Q 4.5 V 6V 2V tt Any Q 4.5 V 6V TA = 25°C MIN TYP MAX 77 26 23 87 27 23 68 24 21 47 23 21 28 8 6 175 35 30 175 35 30 150 30 26 150 30 26 60 12 10 SN54HC573A MIN MAX 265 53 45 265 53 45 225 45 38 225 45 38 90 18 15 SN74HC573A MIN MAX 220 44 38 220 44 38 190 38 32 190 38 32 75 15 13 ns ns ns ns UNIT
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HC573A, SN74HC573A OCTAL TRANSPARENT D TYPE LATCHES WITH 3 STATE OUTPUTS
SCLS147E - DECEMBER 1982 - REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V D tpd LE Any Q Q 4.5 V 6V 2V 4.5 V 6V 2V ten OE Any Q 4.5 V 6V 2V tt Any Q 4.5 V 6V MIN TA = 25°C TYP MAX 95 33 21 103 33 29 85 29 26 60 17 14 200 40 34 225 45 38 200 40 34 210 42 36 SN54HC573A MIN MAX 300 60 51 335 67 57 300 60 51 315 63 53 SN74HC573A MIN MAX 250 50 43 285 57 48 250 50 43 265 53 45 ns ns ns UNIT
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per latch TEST CONDITIONS No load TYP 50 UNIT pF
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