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Part: 8601101EA
Category:
Logic
-> Counters
-> Decade Counters
Description: ti CD54HC4017, High Speed CMOS Logic Decade Counter/divider With 10 Decoded Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 8601101EA datasheet File size : 136 kB
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Datasheet text preview:
CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS
SGDS011 MAY 1999
D D D D D D D D
2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H)
F PACKAGE (TOP VIEW)
5 1 0 2 6 7 3 GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC MR CP CE TC 9 4 8
description
The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low. The CD54HC4017 is characterized for operation over the full military temperature range of 55°C to 125°C.
FUNCTION TABLE INPUTS CP L X X X H CE X H X L X MR L L H L L L L OUTPUT STATE STATE No change No change 0=H 19 = L Increments counter No change No change Increments counter
If n < 5, TC = H; otherwise, TC = L.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303
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1
CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS
SGDS011 MAY 1999
logic diagram (positive logic)
3 0 2 4 7 10 1 5 5 6 6 7 9 8 11 9 12 TC 1 Decoded Decimal Out 2 3 4
D C
Q Q
D C
Q Q
D C
Q Q
D C
Q Q
D C
Q Q
R
R
R
R
R
MR
15
13 CE 14 CP
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS
SGDS011 MAY 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, each output pin, IO (VO > 0.5 V or VO < VCC + 0.5 V) . . . . . . . . . . . . . . ±25 mA VCC or ground current, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating (see Note 1)
MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO tt Low-level input voltage Input voltage Output voltage Input transition (rise and fall) time VCC = 2 V VCC = 4.5 V VCC = 4.5 V VCC = 6 V 2 1.5 3.15 4.2 0 0 0 0 0 0 0 0.5 1.35 1.8 VCC VCC 1000 500 ns V V V V MAX 6 UNIT V
VCC = 6 V 0 400 TA Operating free-air temperature 55 125 °C NOTE 1: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS VCC 2V CMOS loads VOH TTL loads loads VI = VIH or VIL or IOH = 4 mA IOH = 5.2 mA IOL = 0.02 mA IOL = 4 mA IOL = 5.2 mA IO = 0 VI = VIH or VIL, IOH = 0.02 mA 4.5 V 6V 4.5 V 6V 2V CMOS loads VOL TTL loads loads II ICC Ci VI = VIH or VIL or VI = VCC or 0 VI = VCC or 0, VI = VIH or VIL, 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V TA = 25°C MIN MAX 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±100 8 10 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1000 160 10 nA µA pF V V MAX UNIT
POST OFFICE BOX 655303
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3
CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS
SGDS011 MAY 1999
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VCC 2V fclock Maximum clock frequency 4.5 V 6V 2V CP tw Pulse duration duration MR 4.5 V 6V 2V 4.5 V 6V 2V tsu Setup time, CE to CP 4.5 V 6V 2V th Hold time, CE to CP 4.5 V 6V 2V trem Removal time, MR 4.5 V 6V 80 16 14 80 16 14 75 15 13 0 0 0 5 5 5 TA = 25°C MIN MAX 6 30 35 120 24 20 120 24 20 110 22 19 0 0 0 5 5 5 ns ns ns ns MIN MAX 4 20 23 MHz UNIT
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS
SGDS011 MAY 1999
timing requirements
CP
MR CE
0 1 1
0 1
2 3 4 5 6 7
2 3 4 5 6 7
2
8 9
8 9
TC
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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