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Details, datasheet, quote on part number:8601201CA
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| Part: | 8601201CA |
| Category: | Logic => Counters => Binary Counters |
| Description: | ti CD54HC4024, High Speed CMOS Logic 7-Stage Binary Ripple Counter |
| Company: | Texas Instruments, Inc. |
| Datasheet: | Download 8601201CA datasheet File size : 180 kB |
| Request For quote: | Find where to buy 8601201CA
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Datasheet text preview:
CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024
Data sheet acquired from Harris Semiconductor SCHS202C
November 1997 - Revised October 2003
High-Speed CMOS Logic 7-Stage Binary Ripple Counter
Description
The 'HC4024 and 'HCT4024 are 7-stage ripple-carr y binar y counters. All counter stages are master-slave flip-flops. The state of the stage advances one count on the negative transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.
Features
· Fully Static Operation
[ /Title (CD74 HC402 4, CD74 HCT40 24) /Subject (High Speed CMOS
· Buffered Inputs · Common Reset · Negative Edge Clocking · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC4024F3A CD54HCT4024F3A CD74HC4024E CD74HC4024M CD74HC4024MT CD74HC4024M96 CD74HC4024PW CD74HC4024PWR CD74HC4024PWT CD74HCT4024E CD74HCT4024M TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld PDIP 14 Ld SOIC
NOTE: When ordering, use the entire par t number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250.
Pinout
CD54HC4024, CD54HCT4024 (CERDIP) CD74HC4024 (PDIP, SOIC, TSSOP) CD74HCT4024 (PDIP, SOIC) TOP VIEW
CP 1 MR 2 Q7 3 Q6 4 Q5 5 Q4 6 GND 7 14 VCC 13 NC 12 Q1' 11 Q2 10 NC 9 Q3 8 NC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024 Functional Diagram
12 1 11 Q2 9 Q3 6 Q4 5 Q5 MR 2 4 Q6 3 Q7
Q1'
CP
TRUTH TABLE CP COUNT X MR L L H OUTPUT STATE No Change Advance to Next State All Outputs Are Low
H = High Voltage Level, L = Low Voltage Level, X = Don't Care, = Transition from Low to High Level, = Transition from High to Low.
Logic Diagram
1 CP CP Q 1 Q1 CP Q R 2 MR CP Q 2 CP Q R CP Q 3 CP Q R CP Q 4 CP Q R CP Q 5 CP Q R CP Q 6 CP Q R CP Q 7 CP Q R
7 GND 14 VCC Q1' 12 Q2 11 Q3 9 Q4 6 Q5 5 Q6 4 Q7 3
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CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . 86 PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . 113 (Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
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CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT CP, MR UNIT LOADS 0.5
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC.
Prerequisite for Switching Specifications
25oC PARAMETER HC TYPES Maximum Input Pulse Frequency fMAX 2 4.5 6 Input Pulse Width tW 2 4.5 6 Reset Removal Time tREM 2 4.5 6 6 30 35 80 16 14 50 10 9 5 24 29 100 20 17 65 13 11 4 20 24 120 24 20 75 15 13 MHz MHz MHz ns ns ns ns ns ns SYMBOL VCC (V) MIN MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024
Prerequisite for Switching Specifications
PARAMETER Reset Pulse Width SYMBOL tW VCC (V) 2 4.5 6 HCT TYPES Maximum Input Pulse Frequency Input Pulse Width Reset Recovery Time Reset Pulse Width fMAX tW tREC tW 4.5 4.5 4.5 4.5 25 20 10 20 20 25 13 25 16 30 15 30 MHz ns ns ns (Continued) 25oC MIN 80 16 14 MAX -40oC TO 85oC MIN 100 20 17 MAX -55oC TO 125oC MIN 120 24 20 MAX UNITS ns ns ns
Switching Specifications Input tr, tf = 6ns
PARAMETER HC TYPES Propagation Delay Time (Figure 1) CP to Q1' Output CL =15pF CL = 50pF Qn to Qn + 1 tPLH, tPHL CL = 50pF tPLH, tPHL CL = 50pF 2 4.5 5 6 2 4.5 CL =15pF CL = 50pF MR to Qn tPLH, tPHL CL = 50pF 5 6 2 4.5 5 6 Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF 2 4.5 6 Input Capacitance Power Dissipation Capacitance (Notes 3, 4) HCT TYPES Propagation Delay Time (Figure 2) CP to Q1' Output Qn to Qn + 1 tPLH, tPHL tPLH, tPHL tPLH, tPHL CL = 50pF CL =15pF CL = 50pF CL =15pF CL = 50pF CL =15pF 4.5 5 4.5 5 4.5 5 17 6 17 40 15 40 50 19 50 60 22 60 ns ns ns ns ns ns CIN CPD CL = 50pF CL =15pF 5 11 6 14 30 140 28 24 75 15 13 170 34 29 75 15 13 10 175 35 30 95 19 13 215 43 27 95 19 16 10 210 42 36 110 22 19 255 51 43 110 22 19 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF TEST SYMBOL CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
MR to Qn
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