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Part: 8607601EA
Category:
Logic
-> Counters
-> Binary Counters
Description: ti CD54HC163, High Speed CMOS Logic 4-Bit Binary Counter With Synchronous Reset
Company: Texas Instruments, Inc.
Datasheet: Download 8607601EA datasheet File size : 104 kB
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Datasheet text preview:
The CD54HCT161 is obsolete and no longer is supplied. Data sheet acquired from Harris Semiconductor SCHS154D
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
High-Speed CMOS Logic Presettable Counters
Two count enables, PE and TE, in each counter are provided for n-bit cascading. In all counters reset action occurs regardless of the level of the SPE, PE and TE inputs (and the clock input, CP, in the 'HC161 and 'HCT161 types). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will retur n to the nor mal sequence in one count as shown in state diagram. The look-ahead carr y feature simplifies serial cascading of the counters. Both count enable inputs (PE and TE) must be high to count. The TE input is gated with the Q outputs of all four stages so that at the maximum count the ter minal count (TC) output goes high for one clock period. This TC pulse is used to enable the next cascaded stage.
February 1998 - Revised October 2003
Features [ /Title (CD74 HC161 , CD74 HCT16 1, CD74 HC163 , CD74 HCT16 3) /Subject (High Speed CMOS Logic Presettable Counte rs) /Autho r () /Keywords (High Speed CMOS Logic Presettable Counte rs, High Speed
· 'HC161, 'HCT161 4-Bit Binary Counter, Asynchronous Reset · 'HC163, 'HCT163 4-Bit Binary Counter, Synchronous Reset · Synchronous Counting and Loading · Two Count Enable Inputs for n-Bit Cascading · Look-Ahead Carry for High-Speed Counting · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC161F3A CD54HC163F3A CD54HCT163F3A CD74HC161E CD74HC161M CD74HC161MT CD74HC161M96 CD74HC163E CD74HC163M CD74HC163MT CD74HC163M96 CD74HCT161E CD74HCT161M CD74HCT161MT CD74HCT161M96 CD74HCT163E CD74HCT163M CD74HCT163MT CD74HCT163M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Description
The 'HC161, 'HCT161, 'HC163, and 'HCT163 are presettable synchronous counters that feature look-ahead carr y logic for use in high-speed counting applications. The 'HC161 and 'HCT161 are asynchronous reset decade and binar y counters, respectively; the 'HC163 and 'HCT163 devices are decade and binar y counters, respectively, that are reset synchronously with the clock. Counting and parallel presetting are both accomplished synchronously with the negative-to-positive transition of the clock. A low level on the synchronous parallel enable input, SPE, disables counting operation and allows data at the P0 to P3 inputs to be loaded into the counter (provided that the setup and hold requirements for SPE are met). All counters are reset with a low level on the Master Reset input, MR. In the 'HC163 and 'HCT163 counters (synchronous reset types), the requirements for setup and hold time with respect to the clock must be met.
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Pinout
CD54HC161, CD54HCT161, CD54HC163, CD54HCT163 (CERDIP) CD74HC161, CD74HCT161, CD74HC163, CD74HCT163 (PDIP, SOIC) TOP VIEW
MR 1 CP 2 P0 3 P1 4 P2 5 P3 6 PE 7 GND 8 16 VCC 15 TC 14 Q0 13 Q1 12 Q2 11 Q3 10 TE 9 SPE
Functional Diagram
P0 3 SPE CP MR PE TE 9 2 1 7 10 4 P1 5 P2 6 14 13 12 11 15 Q0 Q1 Q2 Q3 TC P3
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CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
MODE SELECT - FUNCTION TABLE FOR 'HC161 AND 'HCT161 INPUTS OPERATING MODE Reset (Clear) Parallel Load MR L H H Count Inhibit H H H CP X X X PE X X X h I (Note 2) X TE X X X h X I (Note 2) SPE X l l h (Note 3) h (Note 3) h (Note 3) Pn X l h X X X OUTPUTS Qn L L H Count qn qn TC L L (Note 1) (Note 1) (Note 1) L
MODE SELECT - FUNCTION TABLE FOR 'HC163 AND 'HCT163 INPUTS OPERATING MODE Reset (Clear) Parallel Load MR l h (Note 3) h (Note 3) Count Inhibit h (Note 3) h (Note 3) h (Note 3) CP X X PE X X X h I (Note 2) X TE X X X h X I (Note 2) SPE X l l h (Note 3) h (Note 3) h (Note 3) Pn X l h X X X OUTPUTS Qn L L H Count qn qn TC L L (Note 1) (Note 1) (Note 1) L
H = High voltage level steady state; L = Low voltage level steady state; h = High voltage level one setup time prior to the Low-to-High clock transition; l = Low voltage level one setup time prior to the Low-to-High clock transition; X = Don't Care; q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition; = Low-to-High clock transition. NOTES: 1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH for HC/HCT161 and 'HC/HCT163). 2. The High-to-Low transition of PE or TE on the 'HC/HCT161 and the 'HC/HCT163 should only occur while CP is HIGH for conventional operation. 3. The Low-to-High transition of SPE on the 'HC/HCT161 and SPE or MR on the 'HC/HCT163 should only occur while CP is HIGH for conventional operation.
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CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 4) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 4. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 V V V V V V V V V V V V V V V V V V µA SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
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CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 5. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 5) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC VI (V) VCC or GND IO (mA) 0 VCC (V) 6 25oC MIN TYP MAX 8 -40oC TO 85oC -55oC TO 125oC MIN MAX 80 MIN MAX 160 UNITS µA
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT P0 - P3 PE CP MR SPE TE UNIT LOADS 0.25 0.65 1.05 0.8 0.5 1.05
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC.
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Others parts begin by 86
86-1
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