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Part: CD54AC161F3A
Category:
Logic
-> Counters
-> Binary Counters
Description: ti CD54AC161, Synchronous Presettable Binary Counters With Asynchronous Reset
Company: Texas Instruments, Inc.
Datasheet: Download CD54AC161F3A datasheet File size : 186 kB
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Datasheet text preview:
CD54AC161, CD74AC161 4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C SEPTEMBER 1998 REVISED MARCH 2003
D D D D D D
Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection per MIL-STD-883, Method 3015
CD54AC161 . . . F PACKAGE CD74AC161 . . . E OR M PACKAGE (TOP VIEW)
description/ordering information
CLR CLK A B C D ENP GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC RCO QA QB QC QD ENT LOAD
The 'AC161 devices are 4-bit binary counters. These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting These devices are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15, with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. ORDERING INFORMATION
TA PACKAGE PDIP E 55°C to 125°C to 125°C SOIC M Tube Tube Tape and reel ORDERABLE PART NUMBER CD74AC161E CD74AC161M CD74AC161M96 TOP-SIDE MARKING CD74AC161E AC161M
CDIP F Tube CD54AC161F3A CD54AC161F3A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
CD54AC161, CD74AC161 4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C SEPTEMBER 1998 REVISED MARCH 2003
FUNCTION TABLE INPUTS CLR L H H H H H CLK X X X ENP X X X h l X ENT X X X h X l LOAD X l l h h h A,B,C,D X l h X X X OUTPUTS Qn L L H Count qn qn RCO L L Note 1 Note 1 Note 1 L FUNCTION Reset (clear) Parallel load load Count Inhibit
H = high level, L = low level, X = don't care, h = high level one setup time prior to the CLK low-to-high transition, l = low level one setup time prior to the CLK low-to-high transition, q = the state of the referenced output prior to the CLK low-to-high transition, and = CLK low-to-high transition. NOTE 1: The RCO output is high when ENT is high and the counter is at terminal count (HHHH).
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CD54AC161, CD74AC161 4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C SEPTEMBER 1998 REVISED MARCH 2003
logic diagram (positive logic)
LOAD ENT ENP 9 10 7 LD CK CLK CLR 2 1 CK R LD 15
RCO
A
3
M1 G2 1, 2T/1C3 G4 3D 4R M1 G2 1, 2T/1C3 G4 3D 4R
14
QA
13
QB
B
4
C
5
M1 G2 1, 2T/1C3 G4 3D 4R
12
QC
D
6
M1 G2 1, 2T/1C3 G4 3D 4R
11
QD
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
CD54AC161, CD74AC161 4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C SEPTEMBER 1998 REVISED MARCH 2003
logic symbol, each D/T flip-flop
LD (Load) TE (Toggle Enable) CK (Clock) M1 G2 1, 2T/1C3 G4 3D 4R Q (Output)
D (Inverted Data) R (Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
CK LD TE LD
TG
TG LD D TG TG TG CK CK TG
Q
CK R The origins of LD and CK are shown in the logic diagram of the overall device.
CK
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
CD54AC161, CD74AC161 4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C SEPTEMBER 1998 REVISED MARCH 2003
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below: 1. Clear outputs to zero (asynchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit
CLR LOAD A B C D CLK ENP ENT QA QB QC QD RCO 12 13 14 15 0 1 2 Inhibit Count Preset
Data Inputs
Data Outputs
Async Clear
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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