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Part: CD54AC164
Category:
Logic
Description:
Company: Texas Instruments, Inc.
Datasheet: Download CD54AC164 datasheet File size : 186 kB
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Datasheet text preview:
CD54/74AC164, CD54/74ACT164
Data sheet acquired from Harris Semiconductor SCHS240A
September 1998 - Revised May 2000
8-Bit Serial-In/Parallel-Out Shift Register
Description
The 'AC164 and 'ACT164 are 8-bit serial-in/parallel-out shift registers with asynchronous reset that utilize Advanced CMOS Logic technology. Data is shifted on the positive edge of the clock (CP). A LOW on the Master Reset (MR) pin resets the shift register and all outputs go to the LOW state regardless of the input conditions. Two Serial Data inputs (DS1 and DS2) are provided; either one can be used as a Data Enable control.
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Features
· Buffered Inputs · Typical Propagation Delay - 6ns at VCC = 5V, TA = 25oC, CL = 50pF · Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 · SCR-Latchup-Resistant CMOS Process and Circuit Design · Speed of Bipolar FASTTM/AS/S with Significantly Reduced Power Consumption · Balanced Propagation Delays · AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply · ±24mA Output Drive Current - Fanout to 15 FASTTM ICs - Drives 50 Transmission Lines
Ordering Information
PART NUMBER CD54AC164F3A CD74AC164E CD74AC164M CD54ACT164F3A CD74ACT164E CD74ACT164M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC
Pinout
CD54AC164, CD54ACT164 (CERDIP) CD74AC164, CD74ACT164 (PDIP, SOIC) TOP VIEW
DS1 1 DS2 2 Q0 3 Q1 4 Q2 5 Q3 6 GND 7
14 VCC 13 Q7 12 Q6 11 Q5 10 Q4 9 MR 8 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FASTTM is a Trademark of Fairchild Semiconductor. Copyright © 2000, Texas Instruments Incorporated
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CD54/74AC164, CD54/74ACT164 Functional Diagram
1 DS1 2 DS2 3 4 5 6 10 11 12 13 9 MR CP 8 GND = 7 VCC = 14 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
MODE SELECT - TRUTH TABLE INPUTS OPERATING MODE RESET (CLEAR) SHIFT MR L H H H H H L h l X q = = = = = = = CP X DS1 X l l h h DS2 X l h l h Q0 L L L L H OUTPUTS Q1 - Q7 L-L q0 - q6 q0 - q6 q0 - q6 q0 - q6
HIGH voltage level steady state. LOW voltage level steady state. HIGH voltage level one setup time prior to the LOW-to_HIGH clock transition. LOW voltage level one setup time prior to the LOW-to-HIGH clock transition. Don't care. Lowercase letters indicate the state of the referenced output prior to the LOW-to-HIGH clock transition. LOW-to-HIGH clock transition.
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CD54/74AC164, CD54/74ACT164
I
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Thermal Information
Thermal Resistance (Typical, Note 5) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 4) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 3. For up to 4 outputs per device, add ±25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. 5. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST CONDITIONS PARAMETER AC TYPES High Level Input Voltage VIH 1.5 3 5.5 Low Level Input Voltage VIL 1.5 3 5.5 High Level Output Voltage VOH VIH or VIL -0.05 -0.05 -0.05 -4 -24 -75 (Note 6, 7) -50 (Note 6, 7) 1.5 3 4.5 3 4.5 5.5 5.5 1.2 2.1 3.85 1.4 2.9 4.4 2.58 3.94 0.3 0.9 1.65 1.2 2.1 3.85 1.4 2.9 4.4 2.48 3.8 3.85 0.3 0.9 1.65 1.2 2.1 3.85 1.4 2.9 4.4 2.4 3.7 3.85 0.3 0.9 1.65 V V V V V V V V V V V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54/74AC164, CD54/74ACT164
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER Low Level Output Voltage SYMBOL VOL VI (V) VIH or VIL IO (mA) 0.05 0.05 0.05 12 24 75 (Note 6, 7) 50 (Note 6, 7) Input Leakage Current Quiescent Supply Current MSI ACT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIH VIL VOH VIH or VIL -0.05 -24 -75 (Note 6, 7) -50 (Note 6, 7) Low Level Output Voltage VOL VIH or VIL 0.05 24 75 (Note 6, 7) 50 (Note 6, 7) Input Leakage Current Quiescent Supply Current MSI Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load NOTES: 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum 50 transmission-line-drive capability at 85oC, 75 at 125oC. II ICC ICC VCC or GND VCC or GND VCC -2.1 0 4.5 to 5.5 4.5 to 5.5 4.5 4.5 5.5 5.5 4.5 4.5 5.5 5.5 5.5 5.5 4.5 to 5.5 2 4.4 3.94 0.8 0.1 0.36 ±0.1 8 2.4 2 4.4 3.8 3.85 0.8 0.1 0.44 1.65 ±1 80 2.8 2 4.4 3.7 3.85 0.8 0.1 0.5 1.65 ±1 160 3 V V V V V V V V V V µA µA mA II ICC VCC or GND VCC or GND 0 VCC (V) 1.5 3 4.5 3 4.5 5.5 5.5 5.5 5.5 25oC MIN MAX 0.1 0.1 0.1 0.36 0.36 ±0.1 8 -40oC TO 85oC MIN MAX 0.1 0.1 0.1 0.44 0.44 1.65 ±1 80 -55oC TO 125oC MIN MAX 0.1 0.1 0.1 0.5 0.5 1.65 ±1 160 UNITS V V V V V V V µA µA
ACT Input Load Table
INPUT DS1, DS2 MR CP UNIT LOAD 0.5 0.74 0.71
NOTE: Unit load is ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC.
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CD54/74AC164, CD54/74ACT164
Prerequisite For Switching Function
-40oC TO 85oC PARAMETER AC TYPES Max. Clock Frequency fMAX 1.5 3.3 (Note 9) 5 (Note 10) MR Pulse Width tW 1.5 3.3 5 CP Pulse Width tW 1.5 3.3 5 Set-up Time tSU 1.5 3.3 5 Hold Time tH 1.5 3.3 5 MR to CP Removal Time tREM 1.5 3.3 5 ACT TYPES Max. Clock Frequency MR Pulse Width CP Pulse Width Set-up Time Hold Time MR to CP Removal Time fMAX tW tW tSU tH tREM 5 (Note 10) 5 5 5 5 5 80 3.9 6.2 2.2 2.6 0 70 4.5 7.1 2.5 3 0 MHz ns ns ns ns ns 7 62 86 49 5.5 3.9 73 8.2 5.9 27 3.1 2.2 27 3.1 2.2 1 1 1 6 54 75 56 6.3 4.5 84 9.4 6.7 31 3.5 2.5 31 3.5 2.5 1 1 1 MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL VCC (V) MIN MAX -55oC TO 125oC MIN MAX UNITS
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
-40oC TO 85oC PARAMETER AC TYPES Propagation Delay, CP to Qn tPLH, tPHL 1.5 3.3 (Note 9) 5 (Note 10) 4.5 3.2 143 15.9 11.4 4.4 3.1 157 17.5 12.5 ns ns ns SYMBOL VCC (V) MIN TYP MAX -55oC TO 125oC MIN TYP MAX UNITS
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